search for: siisellowering

...22 Mar 2016 13:54:55 -0400 > Subject: [PATCH 1/1] AMDGPU,SI: Implement atomic compare and swap > > --- > lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 1 + > lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 + > lib/Target/AMDGPU/CIInstructions.td | 3 +- > lib/Target/AMDGPU/SIISelLowering.cpp | 41 +++++++++++++++ > lib/Target/AMDGPU/SIISelLowering.h | 1 + > lib/Target/AMDGPU/SIInstrInfo.td | 9 ++++ > lib/Target/AMDGPU/SIInstructions.td | 2 +- > test/CodeGen/AMDGPU/global_atomics.ll | 89 ++++++++++++++++++++++++++++++++ > 8 files chang...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This

Hi Christian, Ryan just reported to me that llvm-3.4 is no longer building on OS X Leopard (https://trac.macports.org/ticket/41548). It seems the issue is with a commit that you made back in April (referenced below) which added this to SIISelLowering.cpp: // Adjust the writemask in the node std::vector<SDValue> Ops; Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32)); for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) Ops.push_back(Node->getOperand(i)); Node = (MachineSDNode*)DAG.UpdateNodeOperands(Nod...

Hi, I've prepared patches for both LLVM and Clang to change the datalayout for R600. This may seem like a bold move, but I think it is warranted. R600/SI is a strange architecture in that it uses 64bit pointers but does not support 64 bit arithmetic except for load/store operations that roughly map onto getelementptr. The current datalayout for r600 includes n32:64, which is odd

...on Sequoia <jeremyhu at apple.com> wrote: > Hi Christian, > > Ryan just reported to me that llvm-3.4 is no longer building on OS X Leopard (https://trac.macports.org/ticket/41548). It seems the issue is with a commit that you made back in April (referenced below) which added this to SIISelLowering.cpp: > > // Adjust the writemask in the node > std::vector<SDValue> Ops; > Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32)); > for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) > Ops.push_back(Node->getOperand(i)); > Node = (Machine...

...t;jeremyhu at apple.com> wrote: >> Hi Christian, >> >> Ryan just reported to me that llvm-3.4 is no longer building on OS X Leopard (https://trac.macports.org/ticket/41548). It seems the issue is with a commit that you made back in April (referenced below) which added this to SIISelLowering.cpp: >> >> // Adjust the writemask in the node >> std::vector<SDValue> Ops; >> Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32)); >> for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) >> Ops.push_back(Node->getOperand(i)); &g...

...rget/AMDGPU/R600RegisterInfo.td > llvm/trunk/lib/Target/AMDGPU/R600Schedule.td > llvm/trunk/lib/Target/AMDGPU/SIAssignInterpRegs.cpp > llvm/trunk/lib/Target/AMDGPU/SICodeEmitter.cpp > llvm/trunk/lib/Target/AMDGPU/SIGenRegisterInfo.pl > llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp > llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h > llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td > llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp > llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h > llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td > llvm/trunk/lib/T...