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...that the GP is only used to reach global variables of local scope and the GOT, where the address of global variables of global scope reside. This model assumes that the distance between the GP and the global data area, GOT and local scope variables is defined at link time. __ Evandro Menezes ◊ SiFive ◊ Austin, TX > On Mar 23, 2020, at 6:20, Sam Elliott <selliott at lowrisc.org> wrote: > > Eli, > > Yep, we’re looking at a ROPI/RWPI model for RISC-V and it is shaking out to be fairly similar to this model (though we’ve only been looking at it for 32-bit RISC-V). > &gt...

Hi, Jonathan. > On Jul 21, 2020, at 17:15, Jonathan Roelofs <jonathan_roelofs at apple.com> wrote: > > > >> On Jul 21, 2020, at 1:46 PM, Evandro Menezes <evandro.menezes at sifive.com <mailto:evandro.menezes at sifive.com>> wrote: >> >> >> >>> On Jul 21, 2020, at 14:30, Chris Lattner via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: >>> >>> >>> >>>&gt...

> On Jul 22, 2020, at 18:09, Jonathan Roelofs <jonathan_roelofs at apple.com> wrote: > > > >> On Jul 22, 2020, at 4:31 PM, Evandro Menezes <evandro.menezes at sifive.com <mailto:evandro.menezes at sifive.com>> wrote: >>> Sure, let’s talk about what that end goal should be! Can you give some other examples of where these inconsistencies could be improved? >> >> None specifically comes to the top of my mind, but they are legion, wh...

...ch a goal shouldn't be sneaked in small doses. Then it just adds more inconsistent error reporting to an already inconsistent reporting. If one wants to improve the error reporting in TableGen, let one take it on himself this project, apart from one's other patches. __ Evandro Menezes ◊ SiFive ◊ Austin, TX -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200721/07b74fb6/attachment.html>

...where the addresses are physically separated. Makes sense. This reminds me of rwpi on ARM; it has a sort of similar scheme of referring to data indirectly through a pointer, but it also changes the ABI to keep the pointer in a reserved register. -Eli From: Evandro Menezes <evandro.menezes at sifive.com> Sent: Friday, March 20, 2020 12:28 PM To: Eli Friedman <efriedma at quicinc.com> Cc: Alex Bradbury <asb at lowrisc.org>; llvm-dev <llvm-dev at lists.llvm.org> Subject: [EXT] Re: [llvm-dev] RISC-V LLVM sync-up call 19 Mar 2020 Hi, Eli. If I’m following correctly, there a...

...r your time and responses. If I have inadvertently been rude, please forgive someone new to LLVM? And if your forgiveness stretches that far, perhaps you could clue me on just how I was rude so that I can avoid it in the future? More thanks, JD Jones From: Bruce Hoult [mailto:brucehoult at sifive.com] Sent: Friday, December 14, 2018 1:29 PM To: jjones at prc-hsv.com Cc: LLVM Developers Mailing List <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] LLVM Backend for a platform with no (normal) stack Having your function prologue call malloc() and epilogue call free() (or simila...

Hi all, In RISC-V ISA, the range of conditional branches is within 4KiB. In current implementation, if the branch target is out of range, LLVM MC will issue an error message to tell users it could not resolve the fixup record. I have compared the result with the GNU assembler. GNU assembler will convert the branch to inverted one plus jump to make the branch possible. The range of unconditional

...would like to be considered as an LLVM incubator project. Our code exists at https://github.com/circt as an out-of-tree MLIR project and our group charter can be found at https://github.com/circt/circt/blob/master/README.md. We have weekly discussions with a group of about 20 people from Xilinx, SiFive, Microsoft, PNNL, ETH Zurich, EPFL, Stanford, and Cornell, and welcome additional contributions. This project is still early and we see many elements as highly experimental. At the same time, we feel that the only way to vet these ideas is to build larger systems which will likely take some time...

...gain for your time and responses. If I have inadvertently been rude, please forgive someone new to LLVM? And if your forgiveness stretches that far, perhaps you could clue me on just how I was rude so that I can avoid it in the future? More thanks, JD Jones From: Bruce Hoult [mailto:brucehoult at sifive.com<mailto:brucehoult at sifive.com>] Sent: Friday, December 14, 2018 1:29 PM To: jjones at prc-hsv.com<mailto:jjones at prc-hsv.com> Cc: LLVM Developers Mailing List <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> Subject: Re: [llvm-dev] LLVM Backend for a...

Thanks for your response. Please see below. From: Bruce Hoult [mailto:brucehoult at sifive.com] Sent: Thursday, December 13, 2018 5:58 PM To: jjones at prc-hsv.com Cc: LLVM Developers Mailing List <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] LLVM Backend for a platform with no (normal) stack Do you have a register that you can store a memory address >> yes...

...es can go both forward and backward, and replacing some branch instructions with the branch pairs can then cause other branches to go out of range.  -Hal On 10/5/20 10:20 PM, Kai Wang via llvm-dev wrote: > Correct the title. > > On Tue, Oct 6, 2020 at 11:11 AM Kai Wang <kai.wang at sifive.com > <mailto:kai.wang at sifive.com>> wrote: > > Hi all, > > In RISC-V ISA, the range of conditional branches is within 4KiB. > In current implementation, if the branch target is out of range, > LLVM MC will issue an error message to tell users it co...

...vm-dev at lists.llvm.org> Subject: [EXT] Re: [llvm-dev] RISC-V LLVM sync-up call 19 Mar 2020 Here's the draft proposal for the compact code model on RV. I'd appreciate your feedback before I propose it to the foundation and go about updating the psABI. Thank you, __ Evandro Menezes ◊ SiFive ◊ Austin, TX On Mar 19, 2020, at 8:58, Alex Bradbury via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote: For background on these calls, see <http://lists.llvm.org/pipermail/llvm-dev/2019-September/135087.html>. Reminder: the purpose is to co-or...

...mance using github hosted builds. See https://github.com/circt/circt - Should have a sense of the community that it hopes to eventually foster, and there should be interest from members with different affiliations / organizations. We have weekly meetings with >20 people from Xilinx, Sifive, Microsoft, PNNL, ETH, EPFL, Cornell, and Stanford. Meeting minutes are here: https://docs.google.com/document/d/1fOSRdyZR2w75D87yU2Ma9h2-_lEPL4NxvhJGJd-s5pk/edit# - Should have a feasible path to eventually graduate as a dedicated top-level or sub-project within the LLVM monorepo <...

On Tue, 19 Jun 2018 at 20:46, Bruce Hoult <brucehoult at sifive.com> wrote: > Furthermore .. in the articles you reference, the -DCLS=$(getconf LEVEL1_DCACHE_LINESIZE) is passed when compiling the user's program -- one doing extensive blocked matrix operations -- and not when building the *compiler*. It's worse. At least in the first case, the c...

...ugh that someone is using clang as the assembler driver and we'd pass through -mthumb when they weren't expecting it. Peter On Thu, 15 Nov 2018 at 12:39, Tim Northover via cfe-dev <cfe-dev at lists.llvm.org> wrote: > > On Thu, 15 Nov 2018 at 12:25, Bruce Hoult <brucehoult at sifive.com> wrote: > > OK, I just checked, and -mcpu=cortex-{m3,m4,m7,a7,a9,a15,a53} gives Thumb at -O1, -O1, -Os on the following gcc: > > If anything I'd be inclined to just default to Thumb always. I haven't > checked myself, but rumour has it the icache benefits make it fast...

...ssembler driver and we'd pass through -mthumb when they weren't expecting it. Peter On Thu, 15 Nov 2018 at 12:39, Tim Northover via cfe-dev <cfe-dev at lists.llvm.org<mailto:cfe-dev at lists.llvm.org>> wrote: > > On Thu, 15 Nov 2018 at 12:25, Bruce Hoult <brucehoult at sifive.com<mailto:brucehoult at sifive.com>> wrote: > > OK, I just checked, and -mcpu=cortex-{m3,m4,m7,a7,a9,a15,a53} gives Thumb at -O1, -O1, -Os on the following gcc: > > If anything I'd be inclined to just default to Thumb always. I haven't > checked myself, but rumour...

I've never tried -mcpu=cortex-xyz but I know -march=armv7 defaults to Thumb OK, I just checked, and -mcpu=cortex-{m3,m4,m7,a7,a9,a15,a53} gives Thumb at -O1, -O1, -Os on the following gcc: arm-linux-gnueabihf-gcc (Ubuntu/Linaro 7.3.0-27ubuntu1~18.04) 7.3.0 cortex-m0 fails because it doesn't do hard float. I don't have an eabi compiler around. On Thu, Nov 15, 2018 at 4:14 AM, Tim

On Wed, 8 Apr 2020 at 04:23, Kai Wang <kai.wang at sifive.com> wrote: > If we apply the type system pointed out by Renato, is the vector type <vscale x 1 x i16> legal? If we decide that <vscale x 1 x i16> is a fundamentally impossible type, does it contrary to the philosophy of LLVM IR as reasonably target-independent IR? I do not get t...

...g the Altera (redirected to Intel) website on "LLVM" got no hits, reducing hope. More thanks than I can type, JD -----Original Message----- From: Anton Korobeynikov [mailto:anton at korobeynikov.info] Sent: Saturday, December 15, 2018 8:33 AM To: jjones at prc-hsv.com Cc: brucehoult at sifive.com; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] LLVM Backend for a platform with no (normal) stack Well, since you're having memory, then things are more or less doable – all you need is to create and maintain stack by yourself. This could be done on per-function basi...

July 15, 2019 1:16 PM, "Bruce Hoult" <brucehoult at sifive.com> wrote: > Take, for example, RISC-V. You have 32 registers that, in the base > fixed-length 32 bits long instruction set, are absolutely > interchangeable with each other. No instructions use implicit source > or destination registers, any register can be used for anything. The...