Displaying 20 results from an estimated 62 matches for "sidt".
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2020 Feb 07
0
[RFC PATCH v7 34/78] KVM: x86: intercept the write access on sidt and other emulated instructions
This is needed for the introspection subsystem to track the changes to
descriptor table registers.
Signed-off-by: Adalbert Laz?r <alazar at bitdefender.com>
---
arch/x86/kvm/x86.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 8c6a8d03e41a..6e665341cc80 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -5450,11 +5450,14 @@
2013 Apr 08
3
[PATCH] x86: make IDT read-only
This makes the IDT unconditionally read-only. This primarily removes
the IDT from being a target for arbitrary memory write attacks. It has
an added benefit of also not leaking (via the "sidt" instruction) the
kernel base offset, if it has been relocated.
Signed-off-by: Kees Cook <keescook at chromium.org>
Cc: Eric Northup <digitaleric at google.com>
---
arch/x86/include/asm/fixmap.h | 4 +---
arch/x86/kernel/cpu/intel.c | 15 ---------------
arch/x86/kernel/tr...
2013 Apr 08
3
[PATCH] x86: make IDT read-only
This makes the IDT unconditionally read-only. This primarily removes
the IDT from being a target for arbitrary memory write attacks. It has
an added benefit of also not leaking (via the "sidt" instruction) the
kernel base offset, if it has been relocated.
Signed-off-by: Kees Cook <keescook at chromium.org>
Cc: Eric Northup <digitaleric at google.com>
---
arch/x86/include/asm/fixmap.h | 4 +---
arch/x86/kernel/cpu/intel.c | 15 ---------------
arch/x86/kernel/tr...
2013 Apr 10
1
[PATCH v3] x86: use a read-only IDT alias on all CPUs
Make a copy of the IDT (as seen via the "sidt" instruction) read-only.
This primarily removes the IDT from being a target for arbitrary memory
write attacks, and has the added benefit of also not leaking the kernel
base offset, if it has been relocated.
We already did this on vendor == Intel and family == 5 because of the
F0 0F bug -- re...
2013 Apr 10
1
[PATCH v3] x86: use a read-only IDT alias on all CPUs
Make a copy of the IDT (as seen via the "sidt" instruction) read-only.
This primarily removes the IDT from being a target for arbitrary memory
write attacks, and has the added benefit of also not leaking the kernel
base offset, if it has been relocated.
We already did this on vendor == Intel and family == 5 because of the
F0 0F bug -- re...
2005 Apr 19
0
[PATCH][1/5] x86-64-eax.patch
...tr) : "memory");
host_env.tr_selector = tr;
host_env.tr_limit = sizeof(struct tss_struct);
host_env.tr_base = (unsigned long) &init_tss[cpu];
@@ -358,7 +358,7 @@
error |= __vmwrite(HOST_GS_BASE, host_env->ds_base);
/* Debug */
- __asm__ __volatile__ ("sidt (%%eax) \n" :: "a"(&desc) : "memory");
+ __asm__ __volatile__ ("sidt (%0) \n" :: "a"(&desc) : "memory");
host_env->idtr_limit = desc.size;
host_env->idtr_base = desc.address;
error |= __vmwrite(HOST_IDTR_BASE,...
2004 Nov 19
1
com32: custom int3 handler
...ried:
void int3_handler()
{
put_str("int3!!!");
__asm__("iret");
}
void init_handlers()
{
struct {
unsigned long limit : 16;
unsigned long base : 32;
} __attribute__((packed)) idtr;
__asm__("sidt (%0)" :: "r"(&idtr));
unsigned long *idt = (void*)idtr.base;
idt[3] = int3_handler;
put_str("about to try int3");
anykey();
__asm__("sti");
__asm__("int3");
put_str("DONE!");...
2013 Apr 09
2
[PATCH v2] x86: use fixed read-only IDT
Make a copy of the IDT (as seen via the "sidt" instruction) read-only.
This primarily removes the IDT from being a target for arbitrary memory
write attacks, and has the added benefit of also not leaking the kernel
base offset, if it has been relocated.
Signed-off-by: Kees Cook <keescook at chromium.org>
Cc: Eric Northup <digita...
2013 Apr 09
2
[PATCH v2] x86: use fixed read-only IDT
Make a copy of the IDT (as seen via the "sidt" instruction) read-only.
This primarily removes the IDT from being a target for arbitrary memory
write attacks, and has the added benefit of also not leaking the kernel
base offset, if it has been relocated.
Signed-off-by: Kees Cook <keescook at chromium.org>
Cc: Eric Northup <digita...
2007 Apr 18
3
[RFC, PATCH 10/24] i386 Vmi descriptor changes
...;m" (*dtr))
-#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr))
-#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt))
-
-#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr))
-#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr))
-#define store_tr(tr) __asm__ ("str %0":"=mr" (tr))
-#define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt))
-
/*
* This is the ldt that every process will get unless we need
* something other than this.
*/
extern struct...
2007 Apr 18
3
[RFC, PATCH 10/24] i386 Vmi descriptor changes
...;m" (*dtr))
-#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr))
-#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt))
-
-#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr))
-#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr))
-#define store_tr(tr) __asm__ ("str %0":"=mr" (tr))
-#define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt))
-
/*
* This is the ldt that every process will get unless we need
* something other than this.
*/
extern struct...
2007 Apr 18
0
[PATCH 5/12] desc-cleanup
...;m" (*dtr))
-#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr))
-#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt))
-
-#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr))
-#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr))
-#define store_tr(tr) __asm__ ("str %0":"=mr" (tr))
-#define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt))
+#define load_gdt(dtr) asm volatile("lgdtl %0"::"m" (*dtr))
+#define load_idt(dtr) asm volatile(&qu...
2007 Apr 18
0
[PATCH 5/12] desc-cleanup
...;m" (*dtr))
-#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr))
-#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt))
-
-#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr))
-#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr))
-#define store_tr(tr) __asm__ ("str %0":"=mr" (tr))
-#define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt))
+#define load_gdt(dtr) asm volatile("lgdtl %0"::"m" (*dtr))
+#define load_idt(dtr) asm volatile(&qu...
2007 Apr 18
1
[PATCH 4/14] i386 / Clean up asm and volatile keywords in desc
...;m" (*dtr))
-#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr))
-#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt))
-
-#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr))
-#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr))
-#define store_tr(tr) __asm__ ("str %0":"=mr" (tr))
-#define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt))
+#define load_gdt(dtr) asm volatile("lgdtl %0"::"m" (*dtr))
+#define load_idt(dtr) asm volatile(&qu...
2007 Apr 18
1
[PATCH 4/14] i386 / Clean up asm and volatile keywords in desc
...;m" (*dtr))
-#define load_tr(tr) __asm__ __volatile("ltr %0"::"mr" (tr))
-#define load_ldt(ldt) __asm__ __volatile("lldt %0"::"mr" (ldt))
-
-#define store_gdt(dtr) __asm__ ("sgdt %0":"=m" (*dtr))
-#define store_idt(dtr) __asm__ ("sidt %0":"=m" (*dtr))
-#define store_tr(tr) __asm__ ("str %0":"=mr" (tr))
-#define store_ldt(ldt) __asm__ ("sldt %0":"=mr" (ldt))
+#define load_gdt(dtr) asm volatile("lgdtl %0"::"m" (*dtr))
+#define load_idt(dtr) asm volatile(&qu...
2007 Apr 18
3
[PATCH 1/4] x86 paravirt_ops: create no_paravirt.h for native ops
(Andrew, please sit these in the -mm tree for cooking)
Create a paravirt.h header for (almost) all the critical operations
which need to be replaced with hypervisor calls.
For the moment, this simply includes no_paravirt.h, where all the
native implementations now live.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Zachary Amsden <zach@vmware.com>
2007 Apr 18
3
[PATCH 1/4] x86 paravirt_ops: create no_paravirt.h for native ops
(Andrew, please sit these in the -mm tree for cooking)
Create a paravirt.h header for (almost) all the critical operations
which need to be replaced with hypervisor calls.
For the moment, this simply includes no_paravirt.h, where all the
native implementations now live.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Zachary Amsden <zach@vmware.com>
2007 Dec 06
51
[PATCH 0/19] desc_struct integration
Hi,
this is a series of patches that unify the struct desc_struct and friends
across x86_64 and i386. As usual, it provides paravirt capabilities as a
side-effect for x86_64.
I consider the main goal, namely, of unifying the desc_struct, an ongoing
effort, being this the beginning. A lot of old code has to be touched to
accomplish that.
I don't consider this patch ready for inclusion.
2007 Dec 06
51
[PATCH 0/19] desc_struct integration
Hi,
this is a series of patches that unify the struct desc_struct and friends
across x86_64 and i386. As usual, it provides paravirt capabilities as a
side-effect for x86_64.
I consider the main goal, namely, of unifying the desc_struct, an ongoing
effort, being this the beginning. A lot of old code has to be touched to
accomplish that.
I don't consider this patch ready for inclusion.
2017 Sep 04
0
[PATCH] x86/paravirt: remove no longer used paravirt functions
...ative_load_tls(t, cpu)
@@ -248,7 +247,7 @@ static inline void native_store_gdt(struct desc_ptr *dtr)
asm volatile("sgdt %0":"=m" (*dtr));
}
-static inline void native_store_idt(struct desc_ptr *dtr)
+static inline void store_idt(struct desc_ptr *dtr)
{
asm volatile("sidt %0":"=m" (*dtr));
}
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 9ccac1926587..c5e3e4d6ac16 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -71,11 +71,6 @@ static inline void write_cr3(unsigned long x)
P...