search for: siblings

Displaying 20 results from an estimated 673 matches for "siblings".

2018 Sep 18
1
Re: NUMA issues on virtualized hosts
On 09/17/2018 04:59 PM, Lukas Hejtmanek wrote: > Hello, > > so the current domain configuration: > <cpu mode='host-passthrough'><topology sockets='8' cores='4' threads='1'/><numa><cell cpus='0-3' memory='62000000' /><cell cpus='4-7' memory='62000000' /><cell cpus='8-11'
2014 Jun 02
0
numa support question on centos 6.5
...t;tcp</uri_transport> </uri_transports> </migration_features> <topology> <cells num='2'> <cell id='0'> <cpus num='20'> <cpu id='0' socket_id='0' core_id='0' siblings='0,20'/> <cpu id='1' socket_id='0' core_id='1' siblings='1,21'/> <cpu id='2' socket_id='0' core_id='2' siblings='2,22'/> <cpu id='3' socket_id='0' core_id=...
2013 Aug 27
1
Finding out CPU topology
Hi, I have been trying to find out CPU topology using libvirt. I understand that I can find out the number of cores/sockets/ threads etc through getCapabilities() function. What I am wondering is that is there any function that can provide me the exact topology like how many sockets, how many sockets per core and number of threads per core, if applicable or may be info about numa cells.  Is there
2020 Mar 30
2
Scalar Evolution Expressions Involving Sibling Loops
> I'm not following your example.  If you have two sibling loops with the same parent, one will frequently, but not always dominate the other.  Can you give a specific example of when forming a recurrence between two siblings (without one dominating the other), is useful? The situation can happen with guarded loops or with a user guard like below: if (c) { for (i = 0; i < n; i++) ... } for (j = 0; j < n; j++) ... The specific example that we ran into is described in https://reviews.llvm.org/D75628. Bas...
2017 May 23
2
Odd Virsh Capabilities response
...unit='KiB' size='2048'>0</pages> <distances> <sibling id='0' value='10'/> </distances> <cpus num='8'> <cpu id='0' socket_id='0' core_id='0' siblings='0'/> <cpu id='1' socket_id='1' core_id='0' siblings='1'/> <cpu id='2' socket_id='0' core_id='2' siblings='2'/> <cpu id='3' socket_id='1' core_id='2...
2012 Jul 17
2
[LLVMdev] Switching between sibling/cousin registers via API calls
I have a register hierarchy that looks like a binary tree. v4 -> {v2, v2} -> {s, s}{s, s}(or, {x, y}, {z, w}) I have an instruction that can access the 2nd and/or 4th scalar and an instruction that can access the 1st and/or 3rd scalar. What I need to do is that given the first scalar, I need to be able to select the 2nd scalar, or/and given the 3rd, select the 4th. I define a sibling
2020 Apr 16
2
Scalar Evolution Expressions Involving Sibling Loops
...ect: Re: [llvm-dev] Scalar Evolution Expressions Involving Sibling Loops > I'm not following your example. If you have two sibling loops with the same parent, one will frequently, but not always dominate the other. Can you give a specific example of when forming a recurrence between two siblings (without one dominating the other), is useful? The situation can happen with guarded loops or with a user guard like below: if (c) { for (i = 0; i < n; i++) ... } for (j = 0; j < n; j++) ... The specific example that we ran into is described in https://reviews.llvm.org/D75628. Basically w...
2013 Sep 17
2
Finding out CPU topology.
...side <topology> tag: <topology>       <cells num='1'>         <cell id='0'>           <memory unit='KiB'>3908488</memory>           <cpus num='4'>             <cpu id='0' socket_id='0' core_id='0' siblings='0'/>             <cpu id='1' socket_id='0' core_id='0' siblings='1'/>             <cpu id='2' socket_id='0' core_id='1' siblings='2'/>             <cpu id='3' socket_id='0' core_id='1'...
2020 Mar 30
2
Scalar Evolution Expressions Involving Sibling Loops
Forwarding to the dev list, in case others ran into similar issues and/or have input on this topic. Bardia Mahjour ----- Forwarded by Bardia Mahjour/Toronto/IBM on 2020/03/30 02:25 PM ----- From: Bardia Mahjour/Toronto/IBM To: listmail at philipreames.com Cc: "Michael Kruse" <llvm at meinersbur.de> Date: 2020/03/26 11:47 AM Subject: Scalar Evolution Expressions Involving Sibling
2012 Jul 17
0
[LLVMdev] Switching between sibling/cousin registers via API calls
Hi Micah, This sounds somewhat similar to what ARM uses for the stride-by-two vector load instructions. For example, Tuples2DSpc. While not exactly what you're looking for, perhaps something along those lines would work? -Jim On Jul 17, 2012, at 3:24 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > I have a register hierarchy that looks like a binary tree. >
2020 Apr 17
2
Scalar Evolution Expressions Involving Sibling Loops
...ubject: Re: [llvm-dev] Scalar Evolution Expressions Involving Sibling Loops > I'm not following your example. If you have two sibling loops with the same parent, one will frequently, but not always dominate the other. Can you give a specific example of when forming a recurrence between two siblings (without one dominating the other), is useful? The situation can happen with guarded loops or with a user guard like below: if (c) { for (i = 0; i < n; i++) ... } for (j = 0; j < n; j++) ... The specific example that we ran into is described in https://reviews.llvm.org/D75628. Basically w...
2013 Sep 17
0
Re: libvirt-users Digest, Vol 45, Issue 28
...> ><topology> >? ? ? <cells num='1'> >? ? ? ? <cell id='0'> >? ? ? ? ? <memory unit='KiB'>3908488</memory> >? ? ? ? ? <cpus num='4'> >? ? ? ? ? ? <cpu id='0' socket_id='0' core_id='0' siblings='0'/> >? ? ? ? ? ? <cpu id='1' socket_id='0' core_id='0' siblings='1'/> >? ? ? ? ? ? <cpu id='2' socket_id='0' core_id='1' siblings='2'/> >? ? ? ? ? ? <cpu id='3' socket_id='0' core_id...
2004 Apr 21
1
difference between coxph and cph
...dence intervals differently? I have listed part of the code and part of the results from the 2 functions. Sorry if this question is a repeat, I didn't find it when I searched the archives. ########################################################### # s= Surv(Time1, Time2, censor) #f= coxph(s~ Siblings + Weight.at.age.4) #summary(f) #Call: #coxph(formula = s ~ Siblings + Weight.at.age.4) # n= 132 # exp(coef) exp(-coef) lower .95 upper .95 #Siblings 1.52 0.657 0.815 2.84 #Weight.at.age.4 0.91 1.099 0.772 1.07 ##############################...
2006 Sep 19
0
Effect.Highlight interferes with Effect.toggle
I''m using something like an accordion, but the div containers have some elements in them that use Effect.Highlight (i.e. InPlaceEditor and Ajax.Checkbox, one of my SAU classes). If I click the element that starts the Effect.SlideUp or some other similar effect, and then mouse over an element starting an Effect.Highlight, the highlight cancels the SlideUp. Or, if the Effect.Highlight
2017 May 23
0
Re: Odd Virsh Capabilities response
...size='2048'>0</pages> > <distances> > <sibling id='0' value='10'/> > </distances> > <cpus num='8'> > <cpu id='0' socket_id='0' core_id='0' siblings='0'/> > <cpu id='1' socket_id='1' core_id='0' siblings='1'/> > <cpu id='2' socket_id='0' core_id='2' siblings='2'/> > <cpu id='3' socket_id='1' core...
2005 Nov 12
2
sibling list element reference during list definition
Can the value of a list element be referenced from a sibling list element during list creation without the use of a temporary variable? The following doesn't work but it's the general idea. > list(value = 2, plusplus = $value+1) such that the following would be the output from str() List of 2 $ value : num 2 $ plusplus: num 3
2017 Mar 20
1
CPU Pinning Help
2004 Oct 29
1
CBQ: sibling isolated-classes lend out bandwidth
How can it be, that class 1:3 in my case borrows, when all sibling classes are isolated ? nessus:~# tc -s -d class show dev eth1 class cbq 1: root rate 100Mbit cell 8b (bounded,isolated) prio no-transmit/8 weight 100Mbit allot 1514b level 2 ewma 5 avpkt 1000b maxidle 1us Sent 484 bytes 7 pkts (dropped 0, overlimits 0) borrowed 0 overactions 0 avgidle 77 undertime 0 class cbq 1:1 parent 1:
2013 Mar 17
0
Bug#703266: Xen PCI passthrough: PCI Backend and pci-stub don't own sibling device 0000:00:00.0
Package: xen-utils-4.1 Version: 4.1.4-2 Severity: normal -- System Information: Debian Release: 7.0 ? APT prefers testing ? APT policy: (990, 'testing'), (500, 'testing-updates') Architecture: amd64 (x86_64) Kernel: Linux 3.2.0-4-amd64 (SMP w/4 CPU cores) Locale: LANG=en_US.UTF-8, LC_CTYPE=en_US.UTF-8 (charmap=UTF-8) Shell: /bin/sh linked to /bin/dash Versions of packages
2014 Dec 05
2
[LLVMdev] InlineSpiller.cpp bug?
Hi Quentin, I have rerun the test case on a recent commit, so the numbers have changed. There are also now a few more basic blocks very small basic blocks in the function, and therefore there are some slight differences. I tried to go back to earlier commits, without success for some reason... This is however very similar, except that there becomes two COPYs back to sibling value after the loop.