search for: sibl

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2018 Sep 18
1
Re: NUMA issues on virtualized hosts
On 09/17/2018 04:59 PM, Lukas Hejtmanek wrote: > Hello, > > so the current domain configuration: > <cpu mode='host-passthrough'><topology sockets='8' cores='4' threads='1'/><numa><cell cpus='0-3' memory='62000000' /><cell cpus='4-7' memory='62000000' /><cell cpus='8-11'
2014 Jun 02
0
numa support question on centos 6.5
...t;tcp</uri_transport> </uri_transports> </migration_features> <topology> <cells num='2'> <cell id='0'> <cpus num='20'> <cpu id='0' socket_id='0' core_id='0' siblings='0,20'/> <cpu id='1' socket_id='0' core_id='1' siblings='1,21'/> <cpu id='2' socket_id='0' core_id='2' siblings='2,22'/> <cpu id='3' socket_id='0' core_i...
2013 Aug 27
1
Finding out CPU topology
Hi, I have been trying to find out CPU topology using libvirt. I understand that I can find out the number of cores/sockets/ threads etc through getCapabilities() function. What I am wondering is that is there any function that can provide me the exact topology like how many sockets, how many sockets per core and number of threads per core, if applicable or may be info about numa cells.  Is there
2020 Mar 30
2
Scalar Evolution Expressions Involving Sibling Loops
> I'm not following your example.  If you have two sibling loops with the same parent, one will frequently, but not always dominate the other.  Can you give a specific example of when forming a recurrence between two siblings (without one dominating the other), is useful? The situation can happen with guarded loops or with a user guard like below: if...
2017 May 23
2
Odd Virsh Capabilities response
...;cell id='0'> <memory unit='KiB'>32945368</memory> <pages unit='KiB' size='4'>8236342</pages> <pages unit='KiB' size='2048'>0</pages> <distances> <sibling id='0' value='10'/> </distances> <cpus num='8'> <cpu id='0' socket_id='0' core_id='0' siblings='0'/> <cpu id='1' socket_id='1' core_id='0' sibli...
2012 Jul 17
2
[LLVMdev] Switching between sibling/cousin registers via API calls
...s}{s, s}(or, {x, y}, {z, w}) I have an instruction that can access the 2nd and/or 4th scalar and an instruction that can access the 1st and/or 3rd scalar. What I need to do is that given the first scalar, I need to be able to select the 2nd scalar, or/and given the 3rd, select the 4th. I define a sibling register as a register that has the same parent and a cousin as a register that has the same grandparent. So 'x' is a cousin of 'w' because of the grandparent class and 'x' is a sibling of 'y' because of the parent class. I know I can move to parent/children regi...
2020 Apr 16
2
Scalar Evolution Expressions Involving Sibling Loops
...hjour <bmahjour at ca.ibm.com>, Philip Reames <listmail at philipreames.com>, "llvm-dev at lists.llvm.org" <llvm-dev at lists.llvm.org> Date: 2020/04/16 04:34 PM Subject: [EXTERNAL] RE: [llvm-dev] Scalar Evolution Expressions Involving Sibling Loops Hi Bardia, I am encountering a similar problem and totally agree that getAddExpr shouldn’t generate any assertion error or at least provide condition check. Even if this is something to avoid, would it be better to return nullptr instead of assertion error? Thanks, Jimmy From: llvm-d...
2013 Sep 17
2
Finding out CPU topology.
...side <topology> tag: <topology>       <cells num='1'>         <cell id='0'>           <memory unit='KiB'>3908488</memory>           <cpus num='4'>             <cpu id='0' socket_id='0' core_id='0' siblings='0'/>             <cpu id='1' socket_id='0' core_id='0' siblings='1'/>             <cpu id='2' socket_id='0' core_id='1' siblings='2'/>             <cpu id='3' socket_id='0' core_id='1&...
2020 Mar 30
2
Scalar Evolution Expressions Involving Sibling Loops
...topic. Bardia Mahjour ----- Forwarded by Bardia Mahjour/Toronto/IBM on 2020/03/30 02:25 PM ----- From: Bardia Mahjour/Toronto/IBM To: listmail at philipreames.com Cc: "Michael Kruse" <llvm at meinersbur.de> Date: 2020/03/26 11:47 AM Subject: Scalar Evolution Expressions Involving Sibling Loops Hi Philip, I hope you are doing well. We've recently run into an issue with SCEV in the context of dependence analysis, and would like your opinion on it. Background discussion can be found here https://reviews.llvm.org/D75628#inline-689527. Basically in this case, the dependence...
2012 Jul 17
0
[LLVMdev] Switching between sibling/cousin registers via API calls
...w}) > > I have an instruction that can access the 2nd and/or 4th scalar and an > instruction that can access the 1st and/or 3rd scalar. What I need to do > is that given the first scalar, I need to be able to select the 2nd scalar, > or/and given the 3rd, select the 4th. I define a sibling register as a register > that has the same parent and a cousin as a register that has the same grandparent. > So 'x' is a cousin of 'w' because of the grandparent class and 'x' is a sibling > of 'y' because of the parent class. > > I know I can mo...
2020 Apr 17
2
Scalar Evolution Expressions Involving Sibling Loops
...on would return those values and when), but returning nullptr from getAddExpr or getSCEVAtScope may be problematic since they currently return valid pointers all the time and changing that would be error prone and would increase code complexity. Returning SCEV_Unknown from getAddExpr would seem plausible except that it would not allow for expression simplifications where recurrences over non-dominating loops can get canceled out. Having said that it may still be a reasonable middle-ground solution. Philip, do you have any thoughts on that? Bardia Mahjour From: Jimmy Zhongduo Lin <jimmy.zh...
2013 Sep 17
0
Re: libvirt-users Digest, Vol 45, Issue 28
...> ><topology> >? ? ? <cells num='1'> >? ? ? ? <cell id='0'> >? ? ? ? ? <memory unit='KiB'>3908488</memory> >? ? ? ? ? <cpus num='4'> >? ? ? ? ? ? <cpu id='0' socket_id='0' core_id='0' siblings='0'/> >? ? ? ? ? ? <cpu id='1' socket_id='0' core_id='0' siblings='1'/> >? ? ? ? ? ? <cpu id='2' socket_id='0' core_id='1' siblings='2'/> >? ? ? ? ? ? <cpu id='3' socket_id='0' cor...
2004 Apr 21
1
difference between coxph and cph
...dence intervals differently? I have listed part of the code and part of the results from the 2 functions. Sorry if this question is a repeat, I didn't find it when I searched the archives. ########################################################### # s= Surv(Time1, Time2, censor) #f= coxph(s~ Siblings + Weight.at.age.4) #summary(f) #Call: #coxph(formula = s ~ Siblings + Weight.at.age.4) # n= 132 # exp(coef) exp(-coef) lower .95 upper .95 #Siblings 1.52 0.657 0.815 2.84 #Weight.at.age.4 0.91 1.099 0.772 1.07 ##########################...
2006 Sep 19
0
Effect.Highlight interferes with Effect.toggle
...gleButton(el.getElementsByTagName(''div'')[0],{ handle:el.firstChild, effect:''blind'', effectOptions: {duration: 0.25} }); }); /* Usage: new ToggleButton(element,{ showHTML/hideHTML: when using default, parent, or sibling, the button created will use this as innerHTML visible: start the element visible? toggle: the event handler called when toggle button clicked onShow: hook called after all default actions have taken place. args: event, this: ToggleButton instance onHide: hook called after all...
2017 May 23
0
Re: Odd Virsh Capabilities response
...> > <memory unit='KiB'>32945368</memory> > <pages unit='KiB' size='4'>8236342</pages> > <pages unit='KiB' size='2048'>0</pages> > <distances> > <sibling id='0' value='10'/> > </distances> > <cpus num='8'> > <cpu id='0' socket_id='0' core_id='0' siblings='0'/> > <cpu id='1' socket_id='1' core_id=&...
2005 Nov 12
2
sibling list element reference during list definition
Can the value of a list element be referenced from a sibling list element during list creation without the use of a temporary variable? The following doesn't work but it's the general idea. > list(value = 2, plusplus = $value+1) such that the following would be the output from str() List of 2 $ value : num 2 $ plusplus: num 3 ---------...
2017 Mar 20
1
CPU Pinning Help
2004 Oct 29
1
CBQ: sibling isolated-classes lend out bandwidth
How can it be, that class 1:3 in my case borrows, when all sibling classes are isolated ? nessus:~# tc -s -d class show dev eth1 class cbq 1: root rate 100Mbit cell 8b (bounded,isolated) prio no-transmit/8 weight 100Mbit allot 1514b level 2 ewma 5 avpkt 1000b maxidle 1us Sent 484 bytes 7 pkts (dropped 0, overlimits 0) borrowed 0 overactions 0 avgidle 77 und...
2013 Mar 17
0
Bug#703266: Xen PCI passthrough: PCI Backend and pci-stub don't own sibling device 0000:00:00.0
...ot;/usr/lib/xen-4.1/bin/../lib/python/xen/xend/XendTask.py", line 209, in log_progress ??? retval = func(*args, **kwds) ? File "/usr/lib/xen-4.1/bin/../lib/python/xen/xend/XendDomainInfo.py", line 2925, in _initDomain ??? raise exn VmError: pci: PCI Backend and pci-stub don't own sibling device 0000:00:00.0 of device 0000:04:00.1 Thanks.
2014 Dec 05
2
[LLVMdev] InlineSpiller.cpp bug?
...bers have changed. There are also now a few more basic blocks very small basic blocks in the function, and therefore there are some slight differences. I tried to go back to earlier commits, without success for some reason... This is however very similar, except that there becomes two COPYs back to sibling value after the loop. My apologies [vregs 76->111, 87->122]. 1. The interval for %vreg111 first covers nearly the entire function. Then it gets split into two intervals, where one covers the inner loops, which makes sense. selectOrSplit %vreg111 [68r,400B:1)[400B,688r:6)[688r,752B:4)[752B...