Displaying 12 results from an estimated 12 matches for "shufpdrri".
2008 Nov 17
2
[LLVMdev] Patterns with Multiple Stores
I want to write a pattern that looks something like this:
def : Pat<(unalignedstore (v2f64 VR128:$src), addr:$dst),
(MOVSDmr ADD64ri8(addr:$dst, imm:8), ( SHUFPDrri (VR128:$src,
(MOVSDmr addr:$dst, FR64:$src))), imm:3)
So I want to convert an unaligned vector store to a scalar store, a shuffle
and a scalar store.
There are several question I have:
- Is the imm:3 syntax correct? Basically I want to hard-code the shuffle mask
- The first MOVSD d...
2008 Nov 17
0
[LLVMdev] Patterns with Multiple Stores
On Monday 17 November 2008 14:28, David Greene wrote:
> I want to write a pattern that looks something like this:
>
> def : Pat<(unalignedstore (v2f64 VR128:$src), addr:$dst),
> (MOVSDmr ADD64ri8(addr:$dst, imm:8), ( SHUFPDrri (VR128:$src,
> (MOVSDmr addr:$dst, FR64:$src))), imm:3)
>
> So I want to convert an unaligned vector store to a scalar store, a shuffle
> and a scalar store.
I got a little further with this:
def : Pat<(unalignedstore (v2f64 VR128:$src), addr:$dst),
(MOVSDmr (AD...
2008 Oct 02
0
[LLVMdev] Making Sense of ISel DAG Output
...what I'm trying to do:
let AddedComplexity = 40 in {
def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:
$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:
$src2))),
SHUFP_shuffle_mask:$sm)),
(SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)),
(v2f64 (MOVSD2PDrm addr:$src2)),
SHUFP_shuffle_mask:$sm)>, Requires<[HasSSE2]>;
} // AddedComplexity
It turns out you can't actually write a pattern like this with tblgen as-is.
There's a bug where it...
2008 Oct 02
6
[LLVMdev] Making Sense of ISel DAG Output
...%reg1071<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
> %reg1072<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288, Mem:LD(8,8)
> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
> %reg1073<def> = SHUFPDrri %reg1071, %reg1072, 0 ; srcLine 10
Actrually, it's worse than this. I wanted to check to make sure something
else wasn't causing the problem but it appears to come from isel. The full
output for the DAG looks like this:
%reg1059<def> = MOVSX64rm32 %reg1033, 1, %reg0, 4, Mem:LD...
2008 Oct 02
4
[LLVMdev] Making Sense of ISel DAG Output
I'm debugging some X86 patterns and I want to understand the debug dumps from
isel better.
Here's some example output:
0x391bc40: i64,ch = load 0x3922c50, 0x391b8d0, 0x38dc530 <0x39053e0:0> <sext
i32> alignment=4 srcLineNum= 10
0x3922c50: <multiple use>
0x391bc40: <multiple use>
0x3856ab0: <multiple use>
0x3914520: i64 =
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
...g1026, 8, %reg1065, 4294967288,
>> Mem:LD(8,8)
>> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
>> %reg1072<def> = MOVSD2PDrm %reg1026, 8, %reg1065, 4294967288,
>> Mem:LD(8,8)
>> [r66428 + 0]LD(8,8) [r78427 + 0] ; srcLine 10
>> %reg1073<def> = SHUFPDrri %reg1071, %reg1072, 0 ; srcLine 10
>
> Actrually, it's worse than this. I wanted to check to make sure
> something
> else wasn't causing the problem but it appears to come from isel.
> The full
> output for the DAG looks like this:
>
> %reg1059<def> = M...
2008 Nov 18
1
[LLVMdev] Patterns with Multiple Stores
...008, at 3:50 PM, David Greene wrote:
> On Monday 17 November 2008 14:28, David Greene wrote:
>> I want to write a pattern that looks something like this:
>>
>> def : Pat<(unalignedstore (v2f64 VR128:$src), addr:$dst),
>> (MOVSDmr ADD64ri8(addr:$dst, imm:8), ( SHUFPDrri
>> (VR128:$src,
>> (MOVSDmr addr:$dst, FR64:$src))), imm:3)
>>
>> So I want to convert an unaligned vector store to a scalar store, a
>> shuffle
>> and a scalar store.
>
> I got a little further with this:
>
> def : Pat<(unalignedstore...
2008 Oct 07
2
[LLVMdev] Making Sense of ISel DAG Output
...e following pattern:
let AddedComplexity = 40 in {
def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:
$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:
$src2))),
SHUFP_shuffle_mask:$sm)),
(SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)),
(v2f64 (MOVSD2PDrm addr:$src2)),
SHUFP_shuffle_mask:$sm)>, Requires<[HasSSE2]>;
} // AddedComplexity
After much hacking of tblgen, I finally convinced it to generate some
somewhat-seemingly-reasonably-correct...
2008 Oct 07
0
[LLVMdev] Making Sense of ISel DAG Output
...ty = 40 in {
> def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64
> addr:
> $src1))),
> (v2f64 (scalar_to_vector (loadf64
> addr:
> $src2))),
> SHUFP_shuffle_mask:$sm)),
> (SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)),
> (v2f64 (MOVSD2PDrm addr:$src2)),
> SHUFP_shuffle_mask:$sm)>, Requires<[HasSSE2]>;
> } // AddedComplexity
>
> After much hacking of tblgen, I finally convinced it to generate some
> somewhat-see...
2008 Oct 20
2
[LLVMdev] TableGen Hacking Help
...I've hacked tblgen to handle patterns like this:
let AddedComplexity = 40 in {
def : Pat<(vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:$src2))),
SHUFP_shuffle_mask:$sm),
(SHUFPDrri (MOVSD2PDrm addr:$src1),
(MOVSD2PDrm addr:$src2),
SHUFP_shuffle_mask:$sm)>, Requires<[HasSSE2]>;
} // AddedComplexity
I believe the problem with the tblgen in trunk is that it doesn't know how to
support patterns with two memory operands....
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
On Fri, October 3, 2008 9:10 am, David Greene wrote:
> On Thursday 02 October 2008 19:32, Dan Gohman wrote:
>
>> Looking at your dump() output above, it looks like the pre-selection
>> loads have multiple uses, so even though you've managed to match a
>> larger pattern that incorporates them, they still need to exist to
>> satisfy some other users.
>
> Yes,
2008 Oct 03
3
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 19:32, Dan Gohman wrote:
> Looking at your dump() output above, it looks like the pre-selection
> loads have multiple uses, so even though you've managed to match a
> larger pattern that incorporates them, they still need to exist to
> satisfy some other users.
Yes, I looked at that too. It looks like these other uses end up being
chains to