Displaying 8 results from an estimated 8 matches for "shufp_shuffle_mask".
2008 Oct 07
2
[LLVMdev] Making Sense of ISel DAG Output
...e's what's happening.
I have the following pattern:
let AddedComplexity = 40 in {
def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:
$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:
$src2))),
SHUFP_shuffle_mask:$sm)),
(SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)),
(v2f64 (MOVSD2PDrm addr:$src2)),
SHUFP_shuffle_mask:$sm)>, Requires<[HasSSE2]>;
} // AddedComplexity
After much hacking of tblgen, I finally convinced it to generate some
somewha...
2008 Oct 02
0
[LLVMdev] Making Sense of ISel DAG Output
...send it in a bit.
Ok, here's what I'm trying to do:
let AddedComplexity = 40 in {
def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:
$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:
$src2))),
SHUFP_shuffle_mask:$sm)),
(SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)),
(v2f64 (MOVSD2PDrm addr:$src2)),
SHUFP_shuffle_mask:$sm)>, Requires<[HasSSE2]>;
} // AddedComplexity
It turns out you can't actually write a pattern like this with tblgen as-is.
Th...
2008 Oct 07
0
[LLVMdev] Making Sense of ISel DAG Output
...lowing pattern:
>
> let AddedComplexity = 40 in {
> def : Pat<(v2f64 (vector_shuffle (v2f64 (scalar_to_vector (loadf64
> addr:
> $src1))),
> (v2f64 (scalar_to_vector (loadf64
> addr:
> $src2))),
> SHUFP_shuffle_mask:$sm)),
> (SHUFPDrri (v2f64 (MOVSD2PDrm addr:$src1)),
> (v2f64 (MOVSD2PDrm addr:$src2)),
> SHUFP_shuffle_mask:$sm)>, Requires<[HasSSE2]>;
> } // AddedComplexity
>
> After much hacking of tblgen, I finally convinced it...
2008 Oct 20
2
[LLVMdev] TableGen Hacking Help
...final bit of tblgen hacking.
I've hacked tblgen to handle patterns like this:
let AddedComplexity = 40 in {
def : Pat<(vector_shuffle (v2f64 (scalar_to_vector (loadf64 addr:$src1))),
(v2f64 (scalar_to_vector (loadf64 addr:$src2))),
SHUFP_shuffle_mask:$sm),
(SHUFPDrri (MOVSD2PDrm addr:$src1),
(MOVSD2PDrm addr:$src2),
SHUFP_shuffle_mask:$sm)>, Requires<[HasSSE2]>;
} // AddedComplexity
I believe the problem with the tblgen in trunk is that it doesn't know how to
support patterns wit...
2008 Oct 03
0
[LLVMdev] Making Sense of ISel DAG Output
On Fri, October 3, 2008 9:10 am, David Greene wrote:
> On Thursday 02 October 2008 19:32, Dan Gohman wrote:
>
>> Looking at your dump() output above, it looks like the pre-selection
>> loads have multiple uses, so even though you've managed to match a
>> larger pattern that incorporates them, they still need to exist to
>> satisfy some other users.
>
> Yes,
2008 Oct 03
3
[LLVMdev] Making Sense of ISel DAG Output
On Thursday 02 October 2008 19:32, Dan Gohman wrote:
> Looking at your dump() output above, it looks like the pre-selection
> loads have multiple uses, so even though you've managed to match a
> larger pattern that incorporates them, they still need to exist to
> satisfy some other users.
Yes, I looked at that too. It looks like these other uses end up being
chains to
2008 Oct 02
4
[LLVMdev] Making Sense of ISel DAG Output
I'm debugging some X86 patterns and I want to understand the debug dumps from
isel better.
Here's some example output:
0x391bc40: i64,ch = load 0x3922c50, 0x391b8d0, 0x38dc530 <0x39053e0:0> <sext
i32> alignment=4 srcLineNum= 10
0x3922c50: <multiple use>
0x391bc40: <multiple use>
0x3856ab0: <multiple use>
0x3914520: i64 =
2009 Dec 17
2
[LLVMdev] AVX Shuffles & PatLeaf Help Needed
...ement size and thus
we can't map shufflevector indices valid ranges for output vector elements.
If I change isSHUFPMask to take an extra argument which is the result
vector type (or element type, or something similar), how would I express
that extra argument in the .td file? Right now we do:
SHUFP_shuffle_mask:$src3
to add the predicate to check the 3rd (mask) operand for conformance to
something SHUFPS/D can handle.
Is there some way currently to add another "argument" to the PatLeaf
invocation?
-Dave