search for: shr32r1

...om/spreadsheets/d/11_vFQRpiPHQ3zLcx8cVYYCqR5N5PCa4IvMyKHwF7Op4/edit?usp=sharing> for sandybridge, haswell and skylake processors including diffs with LLVM latencies. Excerpt: sandybridge haswell skylake mnemonic llvm-exegesis TD file llvm-exegesis TD file llvm-exegesis TD file SHR32r1 1.01 1.00 1.00 1.00 1.01 1.00 IMUL16rri 4.02 3.00 4.01 3.00 4.01 3.00 - Some instructions have different implementations depending on which registers are assigned. This is well known for cases like `xor eax, eax` and `xor eax, ebx`, which emits no uops in the first case...

...sandybridge > > > > haswell > > > > skylake > > mnemonic > > > > llvm-exegesis > > > > TD file > > > > llvm-exegesis > > > > TD file > > > > llvm-exegesis > > > > TD file > > SHR32r1 > > > > 1.01 > > > > 1.00 > > > > 1.00 > > > > 1.00 > > > > 1.01 > > > > 1.00 > > IMUL16rri > > > > 4.02 > > > > 3.00 > > > > 4.01 > > > > 3.00 > >...

...and skylake processors including diffs with LLVM > latencies. Excerpt: > > > > sandybridge > > haswell > > skylake > > mnemonic > > llvm-exegesis > > TD file > > llvm-exegesis > > TD file > > llvm-exegesis > > TD file > > SHR32r1 > > 1.01 > > 1.00 > > 1.00 > > 1.00 > > 1.01 > > 1.00 > > IMUL16rri > > 4.02 > > 3.00 > > 4.01 > > 3.00 > > 4.01 > > 3.00 > > > - > > Some instructions have different implementations depending on whic...

...sandybridge > > > > haswell > > > > skylake > > mnemonic > > > > llvm-exegesis > > > > TD file > > > > llvm-exegesis > > > > TD file > > > > llvm-exegesis > > > > TD file > > SHR32r1 > > > > 1.01 > > > > 1.00 > > > > 1.00 > > > > 1.00 > > > > 1.01 > > > > 1.00 > > IMUL16rri > > > > 4.02 > > > > 3.00 > > > > 4.01 > > > > 3.00 > >...

...> >> >> >> TD file >> >> >> >> llvm-exegesis >> >> >> >> TD file >> >> >> >> llvm-exegesis >> >> >> >> TD file >> >> SHR32r1 >> >> >> >> 1.01 >> >> >> >> 1.00 >> >> >> >> 1.00 >> >> >> >> 1.00 >> >> >> >> 1.01 >> >> >> >>...