Displaying 3 results from an estimated 3 matches for "shiftier".
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shifter
2017 May 15
2
Disabling DAGCombine's specific optimization
Hello LLVM Developers,
I am working on an architecture which have one bit shift operation if
barrel shiftier hardware is not present in such cases some DAGCombine
optimizations reduces performance of certain benchmarks upto 5% for example
consider follwing optimization:
fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
Here it introduce 2 shift operations and when barrel shiftier is n...
2017 May 15
2
Disabling DAGCombine's specific optimization
...tic solution.
Cheers
> >
> > On May 15, 2017, at 07:54, vivek pandya via llvm-dev <
> > llvm-dev at lists.llvm.org> wrote:
> >
> > Hello LLVM Developers,
> >
> > I am working on an architecture which have one bit shift operation if
> > barrel shiftier hardware is not present in such cases some DAGCombine
> > optimizations reduces performance of certain benchmarks upto 5% for
> example
> > consider follwing optimization:
> > fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
> > Here it introduce 2 s...
2017 Mar 04
7
Why ISel Shifts operations can only be expanded for Value type vector ?
On Saturday, March 4, 2017, Ryan Taylor <ryta1203 at gmail.com> wrote:
> Why you can't still expand it through MUL with a Custom lowering? Or am I
> missing something?
>
> Yes we can but problem occurs when we know that it is shift with constant
value than if we return ISD::MUL with constant imm operand than LLVM will
convert it to SHL again because the constant will be