Displaying 3 results from an estimated 3 matches for "shfts_a32_imm7".
2020 Jun 04
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
Hi,
I am in the process of porting our target to GlobalISel, and have encountered a problem. Nearly all instructions in our instruction set make modifications to a CC register, and hence are defined as follows:
let ..., Defs = [CCReg] in
def shfts_a32_imm7: Instruction<(outs OurRC:$dst), ...>;
What's more, many of these instructions have patterns where the instruction itself appears inside a nested tree, e.g.:
def Pat<(source pattern ...),
(sext_a32 (INSERT_SUBREG (...), (shfts_a32_imm7 OurRC:$src, Imm7:$imm), ...>;...
2020 Jun 04
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...34 schrieb Gabriel Hjort Åkerlund via llvm-dev:
Hi,
I am in the process of porting our target to GlobalISel, and have
encountered a problem. Nearly all instructions in our instruction set make
modifications to a CC register, and hence are defined as follows:
let ..., Defs = [CCReg] in
def shfts_a32_imm7: Instruction<(outs OurRC:$dst), ...>;
Whats more, many of these instructions have patterns where the instruction
itself appears inside a nested tree, e.g.:
def Pat<(source pattern ...),
(sext_a32 (INSERT_SUBREG (...), (shfts_a32_imm7 OurRC:$src,
Imm7:$imm), ...>;
N...
2020 Jun 08
2
Nested instruction patterns rejected by GlobalISel when having registers in Defs
...tNode1, TARGET_VAL(OurTarget::clearLo32_pseudo), 0,
MVT::i32, 1/*#Ops*/, 5, // Results = #6
/* 61*/ OPC_EmitInteger, MVT::i16, 0,
/* 64*/ OPC_EmitRegister, MVT::i16, 0 /*zero_reg*/,
/* 67*/ OPC_EmitInteger, MVT::i16, 0,
/* 70*/ OPC_EmitNode2, TARGET_VAL(OurTarget::shfts_a32_imm7), 0,
MVT::i32, MVT::i16, 5/*#Ops*/, 6, 1, 7, 8, 9, // Results =
#10 #11
/* 82*/ OPC_EmitInteger, MVT::i32, OurTarget::acc,
/* 85*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
MVT::i40, 3/*#Ops*/, 2, 10, 12, // Results = #13
/* 94*/ OPC_Em...