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Preallocation Instruction Scheduling with Register Pressure Minimization Using a Combinatorial Optimization Approach G. Shobaki, M. Shawabkeh and N. Abu-Rmaileh ACM Transactions on Architecture and Code Optimization (TACO). vol. 10, issue 3, Article 14 (Sept. 2013) http://dx.doi.org/10.1145/2512432 Regards Ghassan Shobaki, PH.D Assistant Professor Department of Computer Science Princess Sumaya University for Technology g dot shobaki...

On Apr 1, 2011, at 2:40 PM, Max Shawabkeh wrote: > Hello llvm-dev, > > I'm doing some experimentation on instruction scheduling and would like to use LLVM as a testbed, by integrating our existing (compiler-agnostic) scheduler into it. I have tinkered enough with the LLVM code to know how to create and run a new scheduler, a...

Hello llvm-dev, I'm doing some experimentation on instruction scheduling and would like to use LLVM as a testbed, by integrating our existing (compiler-agnostic) scheduler into it. I have tinkered enough with the LLVM code to know how to create and run a new scheduler, access the DAG and target info, etc. However, I've come upon some questions that I have been unable to answer so far, and

Hello llvm-dev, I'm currently integrating an experimental instruction scheduler into LLVM and have come upon a point of confusion regarding WAW dependencies. I apologize in advance for the unnecessarily convoluted example, but it's one solid case which fails on my scheduler and where I can get LLVM to produce a graph that shows my question clearly. I have a small piece of code like this