search for: sgprs

...erspective, there is just one sALU and one vALU. Programs written for Southern Islands intermix sALU and vALU instructions and all instructions are executed in order no matter what ALU the are executed on, so there is no synchronization needed between the ALUs. Each ALU has its own register file: SGPRs for sALU, and VGPRs for vALU. The vALU can read from VGPRs and also SGPRs, but the sALU can only read from SGPRs. This restriction on the sALU seems to be causing the instruction selector to generate some illegal copies, which is the main problem I'm trying to solve. For example: NODE0 = ISD...

Hi Escha, Great to have your comment! Do you have any specific reason for not doing like this? I am not sure whether I understand your point correctly. For "just model one thread", do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"?? For my case, may be something like I only need to define r0~r127 as register for i32 register (each r#

Hi, I'm trying to write an LLVM backend for Epiphany arch, and I wonder if someone can give me some advice on how to implement load/store optimization. The CPU itself is 32-bit, but it supports wider 64-bit loads and store. So the basic idea is to make use of those by combining narrow ones. I've checked how it is done in AArch64 and Hexagon, and my current code is very close to the

...lt;escha at apple.com>: > If I understand right, on this arch, ‘uniform’ refers to values that only > take one lane of register file instead of SIMD-width lanes, and they > *share* the same region of the register file as non-uniform values. This is > in contrast to e.g. AMDGPU where SGPRs (scalar GPRs) and VGPRs are separate > register files. > > If this understanding is correct, you may be able to define uniform and > non-uniform registers separately, but make sure that one aliases the other, > e.g. so that (if your SIMD width is 16) VGPR 20 overlaps SGPR 320, > 3...