search for: sfi

Awesome! Thanks so so much! I'm very interested in doing some work with compilers. Yeah, I'm considering writing a research proposal where I work for JIT-SFI, SFI Evasion Technique and Mitigation, and a few other things. Considering your experience working on modifying llvm, what would you say would be a topic where I could start out doing some good work on, either in a new direction or in improving what you have? And how has this research not made it...

I read a lot of white papers, but is there not any open source implementation of SFI or artificial diversity? I google around, but I can't find anywhere anything regarding what I could openly download. In the same respect, I would also like to make an innovation proposal to create such an endeavor if there is not one already. -------------- next part -------------- An HTML atta...

....pdf ). Will it be more helpful to the community if I do the improvements number #1 and #3 mentioned in my previous mail to the mailing list or if i try to port it to arm architecture? I have decided to go ahead with the improvements #1 and #3 that are improving the call graph and porting the KCoFI SFI methods to the ones used in NaCl and PNaCl. It seems to me the community is more interested towards the SFI methods. If the course of the project permits I may also contribute to the fourth improvement that you mentioned. Earlier I mentioned three modifications to improve the KCoFI project. After...

...es, one from the original i386 and another >> from x86_64. This consolidates both entries into a single one. >> >> The logic for x86_32, where this option was not under user control, >> remains identical. On x86_64, PCI_MMCONFIG becomes additionally >> configurable for SFI systems even if ACPI was disabled. This just >> simplifies the logic without restricting the configurability in any way. > > Thanks for mentioning this difference. It's probably trivial, but if > you have any other reason to respin this series, I would split this > into two p...

...ed reference to `llvm::createRelRecoveryPass()' So how do I fix that? Where do I need to be defining this? In addition, when I try to just compile the source files for my pass, I get: llvm[0]: Compiling RelDepInfo.cpp for Debug+Asserts build (PIC) In file included from /x/grwright/llvm/llvm-sfi/RelRecovery/include/RelRecovery.h:20, from RelDepInfo.cpp:1: /x/grwright/llvm/llvm-2.9/include/llvm/LinkAllPasses.h: In constructor ‘<unnamed>::ForcePassLinking::ForcePassLinking()’: /x/grwright/llvm/llvm-2.9/include/llvm/LinkAllPasses.h:152: error: ‘createRelRecoveryPass’ is...

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

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...ndomization (use Google Scholar to find the papers on these technologies). 3) You could enhance the clang static analyzer to perform security-related analyses that have not already been implemented or improve those that already exist. 4) You could implement a Software Fault Isolation system (like SFI, XFI, or BGI (recently published in SOSP 2009)) in LLVM. I'm sure there are many things you can do. I recommend reading up on the security literature and picking something that interests you. If you're interested in SAFECode, please email me off list. Regards, -- John T. > > Am...

Hello, I'm trying to write some backends for LLVM that generate code that complies with SFI validation rules by re-implementing SFI for the LLVM x86 backend based on the Google NaCl project. However, in trying to implement 32-byte code alignment, X86InstrInfo::GetInstSizeInBytes() is returning incorrect instruction sizes for certain instructions (that I have seen so far): MOV32mi, LE...

...| 5 ++-- arch/x86/mm/numa.c | 12 ++++----- arch/x86/mm/numa_emulation.c | 6 ++--- arch/x86/mm/testmmiotrace.c | 5 ++-- arch/x86/oprofile/op_x86_model.h | 6 ++--- arch/x86/platform/olpc/olpc-xo15-sci.c | 2 +- arch/x86/platform/sfi/sfi.c | 3 +-- arch/x86/xen/debugfs.c | 2 +- arch/x86/xen/setup.c | 2 +- 16 files changed, 63 insertions(+), 75 deletions(-) diff --git a/arch/x86/kernel/amd_gart_64.c b/arch/x86/kernel/amd_gart_64.c index 63ff468a7986..6bb37027cd70 100644 --- a/ar...

Sir, I am a M.tech student of Computer Science and Engineering Department ,Indian Institute of technology, Kharagpur(India). I have to do a project in trusted computing field. I went through LLVM Project site. and I want to work in some project of LLVM. Can u suggest me some project which is somehow related to trusted computing and i can work on that ? In hope of your reply, Amit Suthar

...| 12 +++--- arch/x86/mm/numa_emulation.c | 6 +-- arch/x86/mm/testmmiotrace.c | 5 +-- arch/x86/oprofile/op_x86_model.h | 6 +-- arch/x86/platform/olpc/olpc-xo15-sci.c | 2 +- arch/x86/platform/sfi/sfi.c | 3 +- arch/x86/xen/debugfs.c | 2 +- arch/x86/xen/setup.c | 2 +- drivers/acpi/apei/apei-base.c | 32 +++++++-------- drivers/acpi/apei/einj.c | 4 +- drivers/...

...| 12 +++--- arch/x86/mm/numa_emulation.c | 6 +-- arch/x86/mm/testmmiotrace.c | 5 +-- arch/x86/oprofile/op_x86_model.h | 6 +-- arch/x86/platform/olpc/olpc-xo15-sci.c | 2 +- arch/x86/platform/sfi/sfi.c | 3 +- arch/x86/xen/debugfs.c | 2 +- arch/x86/xen/setup.c | 2 +- drivers/acpi/apei/apei-base.c | 32 +++++++-------- drivers/acpi/apei/einj.c | 4 +- drivers/...

...| 12 +++--- arch/x86/mm/numa_emulation.c | 6 +-- arch/x86/mm/testmmiotrace.c | 5 +-- arch/x86/oprofile/op_x86_model.h | 6 +-- arch/x86/platform/olpc/olpc-xo15-sci.c | 2 +- arch/x86/platform/sfi/sfi.c | 3 +- arch/x86/xen/debugfs.c | 2 +- arch/x86/xen/setup.c | 2 +- drivers/acpi/apei/apei-base.c | 32 +++++++-------- drivers/acpi/apei/einj.c | 4 +- drivers/...

...t-release CentOS Linux release 7.1.1503 (Core) # uname -r 3.10.0-123.20.1.el7.x86_64 Hi, We use iSCSI over a 10G Ethernet Adapter and SRP over an Infiniband adapter to provide multipathing to our storage: # lspci | grep 10-Gigabit 81:00.0 Ethernet controller: Intel Corporation 82599ES 10-Gigabit SFI/SFP+ Network Connection (rev 01) 81:00.1 Ethernet controller: Intel Corporation 82599ES 10-Gigabit SFI/SFP+ Network Connection (rev 01) # lspci | grep Mellanox 06:00.0 InfiniBand: Mellanox Technologies MT26428 [ConnectX VPI PCIe 2.0 5GT/s - IB QDR / 10GigE] (rev b0) Originally the HBAs came up as...

...fig.*"), we have two PCI_MMCONFIG entries, one from the original i386 and another from x86_64. This consolidates both entries into a single one. The logic for x86_32, where this option was not under user control, remains identical. On x86_64, PCI_MMCONFIG becomes additionally configurable for SFI systems even if ACPI was disabled. This just simplifies the logic without restricting the configurability in any way. Signed-off-by: Jan Kiszka <jan.kiszka at siemens.com> --- arch/x86/Kconfig | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/x86/Kconfig b/ar...

.....8986a6b6e3df 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2641,8 +2641,10 @@ config PCI_DIRECT depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC || PCI_GOMMCONFIG)) config PCI_MMCONFIG - def_bool y - depends on X86_32 && PCI && (ACPI || SFI) && (PCI_GOMMCONFIG || PCI_GOANY) + bool "Support mmconfig PCI config space access" if X86_64 + default y + depends on PCI && (ACPI || SFI) + depends on X86_64 || (PCI_GOANY || PCI_GOMMCONFIG) config PCI_OLPC def_bool y @@ -2657,11 +2659,6 @@ config PCI_DOMAINS def_...

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -

Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected -