Displaying 6 results from an estimated 6 matches for "sextb".
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sext
2009 Apr 20
4
[LLVMdev] Unnecessary moves after sign-extension in 2-address target
...i16> [#uses=1]
%conv4 = sext i16 %conv3 to i32 ; <i32> [#uses=1]
%add = add i32 %conv1, %c ; <i32> [#uses=1]
%add6 = add i32 %add, %conv4 ; <i32> [#uses=1]
ret i32 %add6
}
And this not-so-great assembler code:
sext:
sextb r1
mov r4,r1 ### unnecessary move
add r4,r3
sextw r2
mov r1,r2 ### unnecessary move
add r1,r4
jmp [r30]
Which should be this:
sext:
sextb r1
add r1,r3
sextw r2
add r1,r2
jmp [r30]
The debug output from LLVM shows this:
********** REWRITING TWO-...
2020 Jan 11
2
[RFC][SDAG] Convert build_vector of ops on extractelts into ops on input vectors
...alization will introduce scalarization code and a subsequent DAG combine
creates an opportunity to remove the scalarization. Here is an example of
that:
define dso_local <2 x i64> @testv(<2 x i64> %a, <2 x i64> %b) {
entry:
%sexta = sext <2 x i64> %a to <2 x i128>
%sextb = sext <2 x i64> %b to <2 x i128>
%mul = mul nsw <2 x i128> %sexta, %sextb
%shift = lshr <2 x i128> %mul, <i128 64, i128 64>
%trunc = trunc <2 x i128> %shift to <2 x i64>
ret <2 x i64> %trunc
}
On PPC, the legalizer will scalarize this since w...
2020 Jan 11
2
[RFC][SDAG] Convert build_vector of ops on extractelts into ops on input vectors
...equent DAG combine
>> creates an opportunity to remove the scalarization. Here is an example of
>> that:
>> define dso_local <2 x i64> @testv(<2 x i64> %a, <2 x i64> %b) {
>> entry:
>> %sexta = sext <2 x i64> %a to <2 x i128>
>> %sextb = sext <2 x i64> %b to <2 x i128>
>> %mul = mul nsw <2 x i128> %sexta, %sextb
>> %shift = lshr <2 x i128> %mul, <i128 64, i128 64>
>> %trunc = trunc <2 x i128> %shift to <2 x i64>
>> ret <2 x i64> %trunc
>> }
>...
2020 Jan 10
2
[RFC][SDAG] Convert build_vector of ops on extractelts into ops on input vectors
I have added a few PPC-specific DAG combines in the past that follow this
pattern on specific operations. Now that it appears that this would be
useful to do on yet another operation, I'm wondering what people think
about doing this in the target-independent DAG Combiner for any
legal/custom operation on the target.
TL; DR;
The generic pattern would look like this:
(build_vector (op
2011 Jun 23
0
[LLVMdev] Instr Description Problem of MCore Backend
Hello
> Finally, I don't know how to describe following instructions in
> MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
> should I use to finish this description?
Do you need the isel support for them? If yes, then you should custom
isel them. iirc ARM and SystemZ backends have similar instructions,
while only the first one supports full isel for them. In
2011 Jun 23
2
[LLVMdev] Instr Description Problem of MCore Backend
Hi, all:
Now I'm working on writing a backend for Moto MCore, but I don't know how to
describe some instructions.
First, I've already written MCoreRegisterInfo.td like these:
class MCoreReg<bits<4> num, string name> : Register<name> {
let Namespace = "MCore";
field bits<4> Num = num;
}
def R0 : MCoreReg< 0, "R0">,