search for: setun

...de = XXXCC::COND_NE; > break; > case ISD::SETUO: > CondCode = XXXCC::COND_UN; > break; > case ISD::SETO: > case ISD::SETUEQ: > case ISD::SETUGT: > case ISD::SETUGE: > case ISD::SETULT: > case ISD::SETULE: > case ISD::SETUNE: > CC = getSetCCInverse(CC,false); > getFPCCtoMBCC(CC,CondCode); > break; > } > } > > I am generating wrong code when using floating point library call for > comparions. For the following simple case: > float branchTest(float a, float b) { > float...

...case ISD::SETONE: case ISD::SETNE: CondCode = XXXCC::COND_NE; break; case ISD::SETUO: CondCode = XXXCC::COND_UN; break; case ISD::SETO: case ISD::SETUEQ: case ISD::SETUGT: case ISD::SETUGE: case ISD::SETULT: case ISD::SETULE: case ISD::SETUNE: CC = getSetCCInverse(CC,false); getFPCCtoMBCC(CC,CondCode); break; } } I am generating wrong code when using floating point library call for comparions. For the following simple case: float branchTest(float a, float b) { float retVal; if (a == b) { retVal = a / b + 22.34; }...

On 03/14/2017 07:16 AM, vivek pandya wrote: > Hello Hal, > setCondCodeAction(expand) for un ordered comparison generates > semantically wrong code for me for example SETUNE gets converted to > SETOE that causes infinite loops. Can you please explain what is happening? It sounds like a bug we should fix. > > What is ideal place where I can convert unordered comparison to un > comparison + OR + ordered comparison ? > Can I do it by adding required S...

...So does this mean if the instruction could set the overflow flag, the instruction should not have [(set ... )] in it's pattern, i see this is the difference in instruction description for the mips case. I'm wondering how llvm knows when to use certain compare instructions such as SETNE or SETUNE? And for sign or zero extending loads? I can see the PatFrags described and the LoadExtType enum defined, and the use of zext and sext to differentiate what containers the values are being loaded into in the IR. Basically I'm trying to describe patterns for automatically selecting between var...

...; .psr abi64 > Cannot yet select: 0x2000000001d76120: i1 = setcc 0x2000000001d46520, > 0x2000000001d48240, 0x2000000001d08fe0 > > FAIL: /dumpster/home/marcel/LLVM/src/llvm/test/CodeGen/Generic/ > 2003-05-27-useboolinotherbb.ll This looks like ia64 backend isn't handling 'setune' (set if unordered or not equal), and looks like an easy place to start. Check out IA64InstrInfo.td, around line 292 for a place to start: def FCMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP: $src2), "fcmp.eq $dst, p0 = $src1, $src2",...

Hi Sam, I am not a MIPS expert by any means, so YMMV, but: MIPS addu only differs to "add" in its (non)setting of the overflow flag. Because LLVM doesn't provide a way via the IR to access the overflow flag, a special notation isn't required in the IR to distinguish the two operations. Do you have another example? Cheers, James -----Original Message----- From:

Thanks for the replies guys but I think I should have phrased my question better... looking at the Mips backend there are machine instructions that operate on signed and unsigned data, such as add and addu. And like Mips, I need to specify unsigned specific instructions, so how do these get chosen between if the LLVM IR does not carry type data? A very general point in the right direction is all i

On May 24, 2008, at 12:12 PM, Bill Wendling wrote: > Let us know if you would like extra eyes on the two PPC failures. Many > of us have a lot of experience with C++. :-) Do you know where these > allocations are? I don't mind if people help out, so here's some information: FAIL: /nfs/llvm/src/llvm/test/Transforms/PredicateSimplifier/ 2006-11-04-ReplacingZeros.ll Failed with

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; - switch (cast<CondCodeSDNode>(CC)->get()) { - case ISD::SETEQ: - case ISD::SETOEQ: - LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; - break; - case ISD::SETNE: - case ISD::SETUNE: - LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; - break; - case ISD::SETGE: - case ISD::SETOGE: - LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; - break; - case ISD::SETLT: - case ISD::SETOLT: - LC1 = (VT == MVT::f32) ?...

...> + SDValue Cond = (isZero(LHS) ? RHS : LHS); > + bool SwapTF = false; > + switch (CCOpcode) { > + case ISD::SETOEQ: > + case ISD::SETUEQ: > + case ISD::SETEQ: > + SwapTF = true; > + // Fall through > + case ISD::SETONE: > + case ISD::SETUNE: > + case ISD::SETNE: > + // We can lower to select > + if (SwapTF) { > + Temp = True; > + True = False; > + False = Temp; > + } > + // CNDE > + return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); > + default...