search for: settargetdagcombine

...ng, and output demarshalling > + setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); > + // We can't return success/failure, only the old value, > + // let LLVM add the comparison > + setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand); > + > setTargetDAGCombine(ISD::FADD); > setTargetDAGCombine(ISD::FSUB); > setTargetDAGCombine(ISD::FMINNUM); > @@ -1168,6 +1174,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { > SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); > r...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This

...'s subreg? Should this be handled in "LowerOperation" or in "PerformDAGCombine"? Or could this be done with a target-independent combine? Would returning true in "isTruncateFree" suffice? Is any lowering code needed at all? The X86 backend seems to do both, "setTargetDAGCombine(ISD::TRUNCATE)", but then also registering a lot of MVTs via "setOperationAction(...,Custom)", depending on things like soft-float. I guess I'm And second: In my case, with only i16 and i8 data types, And are there other truncation operations to be supported? Is there any sce...

...to do (all of this code is in ARMISelLowering.cpp): 0. (You don't actually need to do anything, but I'm just mentioning it FYI.) For selection DAG nodes that are not target-specific, you need to inform the DAG combiner that you want to do some target-specific combining. Look for calls to setTargetDAGCombine() for examples of this. For this case, the relevant nodes are all target-specific, so the DAG combiner will call the target-specific combining hook anyway. 1. Add the ARMISD::VCEQ etc. nodes to the switch in ARMTargetLowering::PerformDAGCombine. 2. Add a function to be called for those compariso...

Hi folks, me again, So, I want to implement a simple optimization in a NEON case I've seen these days, most as a matter of exercise, but it also simplifies (just a bit) the code generated. The case is simple: uint32x2_t x, res; res = vceq_u32(x, vcreate_u32(0)); This will generate the following code: ; zero d16 vmov.i32 d16, #0x0 ; load a

...rationAction(ISD::USUBO, MVT::i32, Custom); > + > // Expand sign extension of vectors > if (!Subtarget->hasBFE()) > setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); > @@ -154,8 +163,6 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : > setTargetDAGCombine(ISD::SELECT_CC); > setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); > > - setOperationAction(ISD::SUB, MVT::i64, Expand); > - > // These should be replaced by UDVIREM, but it does not happen automatically > // during Type Legalization > setOperationAction(ISD::UDIV,...

...tion Selection, this specific node will be target selected to an architecture specific instruction. By 'combination of DAG nodes' I understand 'replacing a set of DAG nodes by an (usually smaller) set of DAG nodes, removing dead nodes and updating all the chains'. I'm using the setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT) and build the new LOAD_VECTOR_EXTRACT node in the PerformDAGCombine(). As per the following trace this work, t59 and params from t58 are merged into t72. During this combination, the chain from t59 to t58 has been merged from new t72 to t57, skipping over t58. So far, so g...