Displaying 20 results from an estimated 63 matches for "setposition".
2011 Feb 13
1
RCytoscape setPosition error
...ape::makeSimpleGraph())
layout (cw, 'jgraph-spring')
redraw(cw)
nodesFr = c('A', 'B', 'C')
nodesTo =c('D', 'E', 'F')
nodesAll = union(nodesFr, nodesTo)
nElemFr = length(nodesFr)
nElemTo = length(nodesTo)
g <- graph::addNode(nodesAll, g)
setPosition(cw, nodesFr , c(400, 400, 400), c(100, 200, 300))
setPosition(cw, nodesTo , c(600, 600, 600), c(100, 200, 300))
Error in convertToR(xmlParse(node, asText = TRUE)) :
faultCode: 0 faultString: Failed to invoke method setNodesPositions in
class tudelft.CytoscapeRPC.CytoscapeRPCCallHandler: null
set...
2008 Sep 06
0
Tab control using FXRuby
..."First Name" ,
nil,LABEL_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_Y)
fld1= FXDataTarget.new("")
fld1a=FXTextField.new(addr,20, fld1, FXDataTarget::ID_VALUE,
FRAME_SUNKEN|LAYOUT_FILL_X|LAYOUT_FILL_Y)
fld1a.connect(SEL_COMMAND) do
puts "fld1 contains #{fld1.value}"
main.setPosition(-10, -10)
end
FXLabel.new(addr, "Surname" , nil,LABEL_NORMAL|LAYOUT_FILL_X|LAYOUT_FILL_Y)
fld2= FXDataTarget.new("")
FXTextField.new(addr,20, fld2, FXDataTarget::ID_VALUE,
FRAME_SUNKEN|LAYOUT_FILL_X|LAYOUT_FILL_Y)
fld2.connect(SEL_COMMAND) do
puts "fld2 contains...
2019 Oct 14
1
[PATCH] gm107/ir: fix loading z offset for layered 3d image bindings
...- su->setDef(i, untypedDst[i]);
+ if (loaded && loaded[0]) {
+ for (int i = 0; i < 4; i++)
+ if (loaded[i])
+ loaded[i]->setDef(0, untypedDst[i]);
+ } else {
+ for (int i = 0; i < 4; i++)
+ su->setDef(i, untypedDst[i]);
- bld.setPosition(su, true);
+ bld.setPosition(su, true);
+ }
// Unpack each component into the typed dsts
int bits = 0;
for (int i = 0; i < 4; bits += format->bits[i], i++) {
if (!typedDst[i])
continue;
+
+ if (loaded && loaded[0])
+ bld.setPosition(l...
2013 Sep 05
1
[LLVMdev] [lld] Modeling ELF FileNodes/ControlNodes (Group's) in lld
...node, and add it
after the command line is processed to the inputGraph.
PS : Does Darwin have a command line option to handle files in the order
specified in the command line for libraries ? If so, then the above
would break
I am planning to support other operations too like
inputElement->setPosition(InputGraph::Top)
inputElement->setPosition(InputGraph::Last)
inputElement->setPosition(InputGraph::Position, <value>)
The user has to explicitly call a seperate api so that the elements are
ordered according to whatever the user wants.
inputGraph->insertInputElementAt(InputGraph::...
2015 Feb 23
2
[Mesa-dev] [PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...au/codegen/nv50_ir_lowering_nvc0.cpp
> index 87e75e1..9767566 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
> @@ -77,8 +77,9 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
> bld.setPosition(i, false);
>
> // 1. Take the source and it up.
> - Value *src[2], *dst[2], *def = i->getDef(0);
> - bld.mkSplit(src, 4, i->getSrc(0));
> + Value *input = i->getSrc(0);
> + Value *src[2], *dst[2], *guess, *def = i->getDef(0);
> + bld.mkSplit(src, 4,...
2016 Sep 30
2
[PATCH v2] nv50/ir: constant fold OP_SPLIT
...size = typeSizeof(i->dType);
+ DataType type = typeOfSize(size / 2, isFloatType(i->dType),
+ isSignedType(i->dType));
+ if (likely(type != TYPE_NONE)) {
+ uint64_t val = imm0.reg.data.u64;
+ uint16_t shift = size * 8;
+ bld.setPosition(i, false);
+ for (int8_t d = 0; i->defExists(d); ++d) {
+ bld.mkMov(i->getDef(d), bld.mkImm(val & ((1 << shift) - 1)), type);
+ val >>= shift;
+ }
+ delete_Instruction(prog, i);
+ }
+ }
+ break;
case OP_MUL:
if...
2015 Jan 11
2
[PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...hole.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> @@ -997,6 +997,79 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
> i->op = OP_MOV;
> break;
> }
> + case OP_CVT: {
> + Storage res;
> + bld.setPosition(i, true); /* make sure bld is init'ed */
> + switch(i->dType) {
> + case TYPE_U16:
> + switch (i->sType) {
> + case TYPE_F32:
> + if (i->saturate)
> + res.data.u16 = util_iround(CLAMP(imm0.reg.data.f32, 0,
> +...
2016 Sep 27
2
[PATCH] nv50/ir: constant fold OP_SPLIT
...++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -920,6 +920,29 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
Instruction *newi = i;
switch (i->op) {
+ case OP_SPLIT: {
+ uint16_t shift = 0;
+ DataType type = TYPE_NONE;
+ bld.setPosition(i, false);
+ if (i->sType == TYPE_U64 || i->sType == TYPE_S64) {
+ shift = 32;
+ type = (i->sType == TYPE_U64) ? TYPE_U32 : TYPE_S32;
+ }
+ if (i->sType == TYPE_U32 || i->sType == TYPE_S32) {
+ shift = 16;
+ type = (i->sType == TYPE_U...
2016 Sep 30
2
[PATCH] nv50/ir: constant fold OP_SPLIT
...@ -920,6 +920,29 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
>> Instruction *newi = i;
>>
>> switch (i->op) {
>> + case OP_SPLIT: {
>> + uint16_t shift = 0;
>> + DataType type = TYPE_NONE;
>> + bld.setPosition(i, false);
>> + if (i->sType == TYPE_U64 || i->sType == TYPE_S64) {
>> + shift = 32;
>> + type = (i->sType == TYPE_U64) ? TYPE_U32 : TYPE_S32;
>> + }
>> + if (i->sType == TYPE_U32 || i->sType == TYPE_S32) {
>> +...
2017 Aug 12
3
[PATCH] nvc0/ir: propagate immediates to CALL input MOVs
...veau/codegen/nv50_ir_lowering_nvc0.cpp
index c8f0701572..861d08af24 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -47,8 +47,25 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
int builtin;
bld.setPosition(i, false);
- bld.mkMovToReg(0, i->getSrc(0));
- bld.mkMovToReg(1, i->getSrc(1));
+
+ // Generate movs to the input regs for the call we want to generate
+ for (int s = 0; i->srcExists(s); ++s) {
+ Instruction *ld = i->getSrc(s)->getInsn();
+ ImmediateValue imm;
+...
2015 Jan 11
2
[PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
....cpp
>>> @@ -997,6 +997,79 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue
>>> &imm0, int s)
>>> i->op = OP_MOV;
>>> break;
>>> }
>>> + case OP_CVT: {
>>> + Storage res;
>>> + bld.setPosition(i, true); /* make sure bld is init'ed */
>>> + switch(i->dType) {
>>> + case TYPE_U16:
>>> + switch (i->sType) {
>>> + case TYPE_F32:
>>> + if (i->saturate)
>>> + res.data.u16 = uti...
2015 Jan 11
2
[PATCH v2] nv50/ir: Handle OP_CVT when folding constant expressions
...e
>>>>>> &imm0, int s)
>>>>>> i->op = OP_MOV;
>>>>>> break;
>>>>>> }
>>>>>> + case OP_CVT: {
>>>>>> + Storage res;
>>>>>> + bld.setPosition(i, true); /* make sure bld is init'ed */
>>>>>> + switch(i->dType) {
>>>>>> + case TYPE_U16:
>>>>>> + switch (i->sType) {
>>>>>> + case TYPE_F32:
>>>>>> + if (i-&...
2013 Sep 05
0
[LLVMdev] [lld] Modeling ELF FileNodes/ControlNodes (Group's) in lld
On Sep 4, 2013, at 9:28 PM, Shankar Easwaran <shankare at codeaurora.org> wrote:
> Hi Nick,
>
> These are the below modifications needed in lld to start processing groups :-
>
> 1) LinkerInput would be moved to FileNode that contains the following functions
> - getBuffer
> - takeBuffer
> - getPath
>
> 2) The driver will process the vector of
2016 Oct 02
2
[PATCH] nv50/ir: Propagate third immediate src when folding OP_MAD
...2));
i->src(0).mod = i->src(2).mod;
i->setSrc(1, NULL);
i->setSrc(2, NULL);
- i->op = i->src(0).mod.getOp();
- if (i->op != OP_CVT)
- i->src(0).mod = 0;
+ if (i->src(0).getImmediate(imm1)) {
+ bld.setPosition(i, false);
+ newi = bld.mkMov(i->getDef(0), bld.mkImm(imm1.reg.data.u64),
+ i->dType);
+ delete_Instruction(prog, i);
+ }
+ else {
+ i->op = i->src(0).mod.getOp();
+ if (i->op != OP_CVT)
+...
2015 Feb 23
2
[PATCH 1/2] nv50/ir: add fp64 support on G200 (NVA0)
...mputes the
+ * appropriate function. As a first guess, we use the "quake" style
+ * approximation for RSQ:
+ *
+ * 0x5fe6eb50c7b537a9 - num >> 1
+ *
+ * For RCP, we will then square it.
+ */
+ Value *abs, *guess, *parts[2], *input[2], *shr[4], *pred;
+
+ bld.setPosition(i, false);
+
+ abs = bld.mkOp1v(OP_ABS, TYPE_F64, bld.getSSA(8), i->getSrc(0));
+
+ parts[0] = bld.loadImm(NULL, 0xc7b537a9);
+ parts[1] = bld.loadImm(NULL, 0x5fe6eb50);
+ guess = bld.mkOp2v(OP_MERGE, TYPE_F64, bld.getSSA(8), parts[0], parts[1]);
+
+ bld.mkSplit(input, 4, abs);
+ shr...
2015 Feb 23
0
[PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 87e75e1..9767566 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -77,8 +77,9 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
bld.setPosition(i, false);
// 1. Take the source and it up.
- Value *src[2], *dst[2], *def = i->getDef(0);
- bld.mkSplit(src, 4, i->getSrc(0));
+ Value *input = i->getSrc(0);
+ Value *src[2], *dst[2], *guess, *def = i->getDef(0);
+ bld.mkSplit(src, 4, input);
// 2. We don't ca...
2015 Jan 11
2
[PATCH v2] nv50/ir: Handle OP_CVT when folding constant expressions
...7,87 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue
>>>> &imm0, int s)
>>>> i->op = OP_MOV;
>>>> break;
>>>> }
>>>> + case OP_CVT: {
>>>> + Storage res;
>>>> + bld.setPosition(i, true); /* make sure bld is init'ed */
>>>> + switch(i->dType) {
>>>> + case TYPE_U16:
>>>> + switch (i->sType) {
>>>> + case TYPE_F32:
>>>> + if (i->saturate)
>>>> +...
2015 Jan 11
2
[PATCH v2] nv50/ir: Handle OP_CVT when folding constant expressions
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> @@ -997,6 +997,87 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
>> i->op = OP_MOV;
>> break;
>> }
>> + case OP_CVT: {
>> + Storage res;
>> + bld.setPosition(i, true); /* make sure bld is init'ed */
>> + switch(i->dType) {
>> + case TYPE_U16:
>> + switch (i->sType) {
>> + case TYPE_F32:
>> + if (i->saturate)
>> + res.data.u16 = util_iround(CLAMP(imm0.reg....
2015 Jan 11
2
[PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...;>>>> ImmediateValue
>>>>> &imm0, int s)
>>>>> i->op = OP_MOV;
>>>>> break;
>>>>> }
>>>>> + case OP_CVT: {
>>>>> + Storage res;
>>>>> + bld.setPosition(i, true); /* make sure bld is init'ed */
>>>>> + switch(i->dType) {
>>>>> + case TYPE_U16:
>>>>> + switch (i->sType) {
>>>>> + case TYPE_F32:
>>>>> + if (i->saturate)
>>...
2015 Feb 23
0
[Mesa-dev] [PATCH 2/2] nvc0/ir: improve precision of double RCP/RSQ results
...owering_nvc0.cpp
>> index 87e75e1..9767566 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
>> @@ -77,8 +77,9 @@ NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
>> bld.setPosition(i, false);
>>
>> // 1. Take the source and it up.
>> - Value *src[2], *dst[2], *def = i->getDef(0);
>> - bld.mkSplit(src, 4, i->getSrc(0));
>> + Value *input = i->getSrc(0);
>> + Value *src[2], *dst[2], *guess, *def = i->getDef(0);
>>...