search for: setos

Displaying 20 results from an estimated 34 matches for "setos".

Did you mean: setosa
2012 Jul 10
1
[LLVMdev] floating point: seto opcode
Hi, Given the following in ISDOpcodes.h SETO, // 0 1 1 1 True if ordered (no nans) SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) Is it safe to assume that SETO is not of SETUO? We have support for setuo in the architecture but not seto. Sirish -------------- next part -------------- An HTML attachment was scrubbed...
2012 Sep 18
3
R: [PATCH 2/2] Btrfs-progs: add mount-option command
Hi Seto, please could you update also the man page too ? Why it was not provided a way to clear a *single* flag ? To me it seems a bit too long to clear all the flag (btrfs mount-option clear) and then set the right one. As user interface I suggest something like chmod: btrfs mount-option set +ssd,skip_balance -nodatacow /dev/sdX or btrfs mount-option set =ssd,skip_balance,nodatacow
2008 Jul 16
2
[PATCH] stopmachine: add stopmachine_timeout v2
Thank you for useful feedbacks! Here is the updated version. Could you put this on top of your patches, Rusty? Thanks, H.Seto If stop_machine() invoked while one of onlined cpu is locked up by some reason, stop_machine cannot finish its work because the locked cpu cannot stop. This means all other healthy cpus will be blocked infinitely by one dead cpu. This patch allows stop_machine to
2008 Jul 16
2
[PATCH] stopmachine: add stopmachine_timeout v2
Thank you for useful feedbacks! Here is the updated version. Could you put this on top of your patches, Rusty? Thanks, H.Seto If stop_machine() invoked while one of onlined cpu is locked up by some reason, stop_machine cannot finish its work because the locked cpu cannot stop. This means all other healthy cpus will be blocked infinitely by one dead cpu. This patch allows stop_machine to
2013 Sep 05
3
[PATCH v2 0/3] btrfs-progs: prevent mkfs from aborting with small volume
Here are 3 patches to avoid undesired aborts of mkfs.btrfs. These are based on top of Chris''s btrfs-progs.git: git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-progs.git Thanks, H.Seto Hidetoshi Seto (3): btrfs-progs: error if device for mkfs is too small btrfs-progs: error if device have no space to make primary chunks btrfs-progs: calculate available
2011 Aug 17
2
[PATCH] btrfs: fix d_off in the first dirent
Since the d_off in the first dirent for "." (that originates from the 4th argument "offset" of filldir() for the 2nd dirent for "..") is wrongly assigned in btrfs_real_readdir(), telldir returns same offset for different locations. | # mkfs.btrfs /dev/sdb1 | # mount /dev/sdb1 fs0 | # cd fs0 | # touch file0 file1 | # ../test | telldir: 0 | readdir: d_off = 2,
2018 Nov 20
2
A pattern for portable __builtin_add_overflow()
Hi LLVM, clang, I'm trying to write a portable version of __builtin_add_overflow() it a way that the compiler would recognize the pattern and use the add_overflow intrinsic / the best possible machine instruction. Here are docs about these builtins: https://clang.llvm.org/docs/LanguageExtensions.html#checked-arithmetic-builtins . With unsigned types this is easy: int uaddo_native(unsigned
2008 Jul 17
1
[PATCH] stopmachine: add stopmachine_timeout v4
If stop_machine() invoked while one of onlined cpu is locked up by some reason, stop_machine cannot finish its work because the locked cpu cannot stop. This means all other healthy cpus will be blocked infinitely by one dead cpu. This patch allows stop_machine to return -EBUSY with some printk messages if any of stop_machine's threads cannot start running on its target cpu in time. You can
2008 Jul 17
1
[PATCH] stopmachine: add stopmachine_timeout v4
If stop_machine() invoked while one of onlined cpu is locked up by some reason, stop_machine cannot finish its work because the locked cpu cannot stop. This means all other healthy cpus will be blocked infinitely by one dead cpu. This patch allows stop_machine to return -EBUSY with some printk messages if any of stop_machine's threads cannot start running on its target cpu in time. You can
2008 Jul 15
2
[LLVMdev] Regarding ARM CodeGen
Hi Evan, Thanks for the answers. I had few more queries though. 1. As far as I was able to understand the Codegen infrastructure, ARMInstrInfo.td file has complete description of the instructions which modify the status flags. For example, we have description for both ADD and ADDS. But the problem is that in LLVM, we have a single "ADD" Instruction. Thus when we do getDesc(add), we get
2008 Jul 15
0
[LLVMdev] Regarding ARM CodeGen
On Jul 14, 2008, at 5:10 PM, kapil anand wrote: > Hi Evan, > > Thanks for the answers. I had few more queries though. > > 1. As far as I was able to understand the Codegen infrastructure, > ARMInstrInfo.td file has complete description of the instructions > which modify the status flags. For example, we have description for > both ADD and ADDS. But the problem is
2008 Jul 14
1
[PATCH] stopmachine: add stopmachine_timeout
On Monday 14 July 2008 21:51:25 Christian Borntraeger wrote: > Am Montag, 14. Juli 2008 schrieb Hidetoshi Seto: > > + /* Wait all others come to life */ > > + while (cpus_weight(prepared_cpus) != num_online_cpus() - 1) { > > + if (time_is_before_jiffies(limit)) > > + goto timeout; > > + cpu_relax(); > > + } > > + > > Hmm. I think this could
2008 Jul 14
1
[PATCH] stopmachine: add stopmachine_timeout
On Monday 14 July 2008 21:51:25 Christian Borntraeger wrote: > Am Montag, 14. Juli 2008 schrieb Hidetoshi Seto: > > + /* Wait all others come to life */ > > + while (cpus_weight(prepared_cpus) != num_online_cpus() - 1) { > > + if (time_is_before_jiffies(limit)) > > + goto timeout; > > + cpu_relax(); > > + } > > + > > Hmm. I think this could
2017 Mar 14
2
Help understanding and lowering LLVM IDS conditional codes correctly
On 03/14/2017 07:16 AM, vivek pandya wrote: > Hello Hal, > setCondCodeAction(expand) for un ordered comparison generates > semantically wrong code for me for example SETUNE gets converted to > SETOE that causes infinite loops. Can you please explain what is happening? It sounds like a bug we should fix. > > What is ideal place where I can convert unordered comparison to un
2011 Dec 19
2
[LLVMdev] Disassembly arbitrary machine-code byte arrays
...;getInstruction(Inst, Size, *Buffer.take(), 0, llvm::nulls(), llvm::nulls()); // llvm::StringRef TheArchString("arm-apple-darwin"); // std::string normalized = llvm::Triple::normalize(TheArchString); // // llvm::Triple TheTriple; // TheTriple.setArch(llvm::Triple::arm); // TheTriple.setOS(llvm::Triple::Darwin); // TheTriple.setVendor(llvm::Triple::Apple); // llvm::Target *TheTarget = NULL; return 0; }
2017 Mar 09
2
Help understanding and lowering LLVM IDS conditional codes correctly
On Thu, Mar 9, 2017 at 9:35 PM, Hal Finkel <hfinkel at anl.gov> wrote: > > On 02/25/2017 03:06 AM, vivek pandya via llvm-dev wrote: > > Note: Question is written after describing what I have coded. > > Hello LLVMDevs, > > I am trying to impliment floating point comparsion for an architecture > which > supports following type of floating point comparision if FPU
2014 Jun 19
2
[LLVMdev] [PATCH] triples for baremetal
...:MachO) || StringRef(CPUName).startswith("cortex-m")) { ABIName = "aapcs"; @@ -5128,7 +5128,7 @@ if (Str == "x86_64h") T.setArchName(Str); else if (Str == "armv6m" || Str == "armv7m" || Str == "armv7em") { - T.setOS(llvm::Triple::UnknownOS); + T.setOS(llvm::Triple::NoneOS); T.setObjectFormat(llvm::Triple::MachO); } } Index: test/Driver/macho-embedded.c =================================================================== --- test/Driver/macho-embedded.c (revision 211122) +++ test/Driver/macho-embedde...
2008 Jul 14
0
[LLVMdev] Regarding ARM CodeGen
On Jul 14, 2008, at 12:59 PM, kapil anand wrote: > Hi all, > > I am using LLVM compiler and CodeGen for generating ARM binaries. > > I was going through the code for ARM backend. I noticed that the ARM > Condition field( Bits 31-28) is generated by converting the > conditions used in icmp and branch. For example, if I have following > C Code > > int a,b,c,d;
2011 Dec 19
0
[LLVMdev] Disassembly arbitrary machine-code byte arrays
...;getInstruction(Inst, Size, *Buffer.take(), 0, llvm::nulls(), llvm::nulls()); // llvm::StringRef TheArchString("arm-apple-darwin"); // std::string normalized = llvm::Triple::normalize(TheArchString); // // llvm::Triple TheTriple; // TheTriple.setArch(llvm::Triple::arm); // TheTriple.setOS(llvm::Triple::Darwin); // TheTriple.setVendor(llvm::Triple::Apple); // llvm::Target *TheTarget = NULL; return 0; } _______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvmde...
2008 Jul 14
2
[LLVMdev] Regarding ARM CodeGen
Hi all, I am using LLVM compiler and CodeGen for generating ARM binaries. I was going through the code for ARM backend. I noticed that the ARM Condition field( Bits 31-28) is generated by converting the conditions used in icmp and branch. For example, if I have following C Code int a,b,c,d; c = a+b; if(c==0) d = a + 10; Then I get ( Assembly Instructions with opcodes only) add *cmp*