search for: setolt

Displaying 8 results from an estimated 8 matches for "setolt".

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2013 Jul 09
2
[LLVMdev] Floating point ordered and unordered comparisons
Hi All, I noticed LLVM target independent side is converting an ordered less than "setolt" into unordered greater than "setuge" operation. There are no target hooks to control going from the ordered mode into unordered. I am trying to figure out the best way to support unordered operation on Hexagon. We don't have a single instruction to do unordered operation. So w...
2017 Feb 25
2
Help understanding and lowering LLVM IDS conditional codes correctly
...condition!"); case ISD::SETEQ: case ISD::SETOEQ: CondCode = XXXCC::COND_E; break; case ISD::SETGT: case ISD::SETOGT: CondCode = XXXCC::COND_GT; break; case ISD::SETGE: case ISD::SETOGE: CondCode = XXXCC::COND_GE; break; case ISD::SETOLT: case ISD::SETLT: CondCode = XXXCC::COND_LT; break; case ISD::SETOLE: case ISD::SETLE: CondCode = XXXCC::COND_LE; break; case ISD::SETONE: case ISD::SETNE: CondCode = XXXCC::COND_NE; break; case ISD::SETUO: CondCode = XXXCC::COND_UN;...
2017 Mar 09
2
Help understanding and lowering LLVM IDS conditional codes correctly
...SETOEQ: > CondCode = XXXCC::COND_E; > break; > case ISD::SETGT: > case ISD::SETOGT: > CondCode = XXXCC::COND_GT; > break; > case ISD::SETGE: > case ISD::SETOGE: > CondCode = XXXCC::COND_GE; > break; > case ISD::SETOLT: > case ISD::SETLT: > CondCode = XXXCC::COND_LT; > break; > case ISD::SETOLE: > case ISD::SETLE: > CondCode = XXXCC::COND_LE; > break; > case ISD::SETONE: > case ISD::SETNE: > CondCode = XXXCC::COND_NE; > break...
2013 Jul 09
0
[LLVMdev] Floating point ordered and unordered comparisons
On Tue, Jul 9, 2013 at 3:00 PM, <sundeepk at codeaurora.org> wrote: > Hi All, > > I noticed LLVM target independent side is converting an ordered less than > "setolt" into unordered greater than "setuge" operation. There are no > target hooks to control going from the ordered mode into unordered. > > I am trying to figure out the best way to support unordered operation on > Hexagon. We don't have a single instruction to do unorde...
2017 Mar 14
2
Help understanding and lowering LLVM IDS conditional codes correctly
...; case ISD::SETOGT: >> CondCode = XXXCC::COND_GT; >> break; >> case ISD::SETGE: >> case ISD::SETOGE: >> CondCode = XXXCC::COND_GE; >> break; >> case ISD::SETOLT: >> case ISD::SETLT: >> CondCode = XXXCC::COND_LT; >> break; >> case ISD::SETOLE: >> case ISD::SETLE: >> CondCode = XXXCC::COND_LE; >> break; >> ca...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...case ISD::SETNE: - case ISD::SETUNE: - LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; - break; - case ISD::SETGE: - case ISD::SETOGE: - LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; - break; - case ISD::SETLT: - case ISD::SETOLT: - LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; - break; - case ISD::SETLE: - case ISD::SETOLE: - LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; - break; - case ISD::SETGT: - case ISD::SETOGT: - LC1 = (VT == MVT::f32) ?...