Displaying 8 results from an estimated 8 matches for "setogt".
Did you mean:
setgt
2008 Nov 11
0
[LLVMdev] Invalid comparison instruction generation
...; do I convert all ule into olt and swap?
The existing legalization infrastructure for condition codes is in
SelectionDAGLegalize::LegalizeSetCCCondCode. If this isn't flexible
enough, you might need to modify it a bit. You should be able to just
do something like "setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);"
for the unsupported comparisons, and let Legalize should take care of
the rest.
Oh, and it looks like there's a legitimate bug in
DAGCombiner::visitXOR: it needs to check whether condition codes are
legal before transforming them.
-Eli
2017 Feb 25
2
Help understanding and lowering LLVM IDS conditional codes correctly
...llowing:
static void getFPCCtoXXCC(ISD::CondCode CC, XXXCC::CondCodes &CondCode) {
switch (CC) {
default:
llvm_unreachable("Unknown FP condition!");
case ISD::SETEQ:
case ISD::SETOEQ:
CondCode = XXXCC::COND_E;
break;
case ISD::SETGT:
case ISD::SETOGT:
CondCode = XXXCC::COND_GT;
break;
case ISD::SETGE:
case ISD::SETOGE:
CondCode = XXXCC::COND_GE;
break;
case ISD::SETOLT:
case ISD::SETLT:
CondCode = XXXCC::COND_LT;
break;
case ISD::SETOLE:
case ISD::SETLE:
CondCode = XXXCC::COND_LE...
2008 Nov 11
4
[LLVMdev] Invalid comparison instruction generation
Eli,
Using the variables from the original IR,
assuming tmp == tmp1 and assume the value is not nan
ogt(tmp, tmp1) is !isnan(tmp) && !isnan(tmp1) && tmp > tmp1, or false
ule(tmp, tmp1) is isnan(tmp) || isnan(tmp1) || tmp <= tmp1, or true
So, this is invalid, or am I misunderstanding what ogt and ule stand
for?
Assuming this is valid, why convert comparison instructions
2017 Mar 09
2
Help understanding and lowering LLVM IDS conditional codes correctly
...dCode CC, XXXCC::CondCodes &CondCode) {
> switch (CC) {
> default:
> llvm_unreachable("Unknown FP condition!");
> case ISD::SETEQ:
> case ISD::SETOEQ:
> CondCode = XXXCC::COND_E;
> break;
> case ISD::SETGT:
> case ISD::SETOGT:
> CondCode = XXXCC::COND_GT;
> break;
> case ISD::SETGE:
> case ISD::SETOGE:
> CondCode = XXXCC::COND_GE;
> break;
> case ISD::SETOLT:
> case ISD::SETLT:
> CondCode = XXXCC::COND_LT;
> break;
> case ISD::SETOL...
2017 Mar 14
2
Help understanding and lowering LLVM IDS conditional codes correctly
...gt;> llvm_unreachable("Unknown FP condition!");
>> case ISD::SETEQ:
>> case ISD::SETOEQ:
>> CondCode = XXXCC::COND_E;
>> break;
>> case ISD::SETGT:
>> case ISD::SETOGT:
>> CondCode = XXXCC::COND_GT;
>> break;
>> case ISD::SETGE:
>> case ISD::SETOGE:
>> CondCode = XXXCC::COND_GE;
>> break;
>> case ISD::SETOLT:
>> c...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...case ISD::SETLT:
- case ISD::SETOLT:
- LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
- break;
- case ISD::SETLE:
- case ISD::SETOLE:
- LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
- break;
- case ISD::SETGT:
- case ISD::SETOGT:
- LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
- break;
- case ISD::SETUO:
- LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
- break;
- case ISD::SETO:
- LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
- break;
- d...