search for: seto

Hi, Given the following in ISDOpcodes.h SETO, // 0 1 1 1 True if ordered (no nans) SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) Is it safe to assume that SETO is not of SETUO? We have support for setuo in the architecture but not seto. Sirish -------------- next part ---------...

Hi Seto, please could you update also the man page too ? Why it was not provided a way to clear a *single* flag ? To me it seems a bit too long to clear all the flag (btrfs mount-option clear) and then set the right one. As user interface I suggest something like chmod: btrfs mount-option set +ssd...

Thank you for useful feedbacks! Here is the updated version. Could you put this on top of your patches, Rusty? Thanks, H.Seto If stop_machine() invoked while one of onlined cpu is locked up by some reason, stop_machine cannot finish its work because the locked cpu cannot stop. This means all other healthy cpus will be blocked infinitely by one dead cpu. This patch allows stop_machine to return -EBUSY with some printk...

Thank you for useful feedbacks! Here is the updated version. Could you put this on top of your patches, Rusty? Thanks, H.Seto If stop_machine() invoked while one of onlined cpu is locked up by some reason, stop_machine cannot finish its work because the locked cpu cannot stop. This means all other healthy cpus will be blocked infinitely by one dead cpu. This patch allows stop_machine to return -EBUSY with some printk...

Here are 3 patches to avoid undesired aborts of mkfs.btrfs. These are based on top of Chris''s btrfs-progs.git: git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-progs.git Thanks, H.Seto Hidetoshi Seto (3): btrfs-progs: error if device for mkfs is too small btrfs-progs: error if device have no space to make primary chunks btrfs-progs: calculate available blocks on device properly ctree.h | 8 +++++ mkfs.c | 23 +++++++++++++ volumes.c | 104 ++++++++...

...= 2, d_name = ".." | telldir: 2 | readdir: d_off = 3, d_name = "file0" : At the moment the "offset" for "." is unused because there is no preceding dirent, however it is better to pass filp->f_pos to follow grammatical usage. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> --- fs/btrfs/inode.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index 15fceef..9c1297b 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -4125,7 +4125,8 @@ static int btrfs_real_readdi...

...(unsigned)b; return (a > 0) ? *s <= b : *s > b; } int saddo_portable2(int a, int b, int* s) { *s = (unsigned)a + (unsigned)b; int cond = a > 0; int check = *s > b; return (cond & !check) | (!cond & check); } Assembly: saddo_native: # @saddo_native xor eax, eax add edi, esi seto al mov dword ptr [rdx], edi ret saddo_portable: # @saddo_portable lea eax, [rsi + rdi] mov dword ptr [rdx], eax cmp eax, esi setle al setg cl test edi, edi jg .LBB3_2 mov eax, ecx .LBB3_2: movzx eax, al ret saddo_portable2: # @saddo_portable2 lea eax, [rsi + rdi] mov dword ptr [rdx], eax test edi,...

...only on smp. v3: - set stopmachine_timeout default to 0 (= never timeout) v2: - remove fix for warning since it will be fixed upcoming typesafe patches - make stopmachine_timeout from secs to msecs - allow disabling timeout by setting the stopmachine_timeout to 0 Signed-off-by: Hidetoshi Seto <seto.hidetoshi at jp.fujitsu.com> --- include/linux/stop_machine.h | 3 ++ kernel/stop_machine.c | 54 +++++++++++++++++++++++++++++++++++++++-- kernel/sysctl.c | 12 +++++++++ 3 files changed, 66 insertions(+), 3 deletions(-) diff --git a/include/linux/stop_mach...

...only on smp. v3: - set stopmachine_timeout default to 0 (= never timeout) v2: - remove fix for warning since it will be fixed upcoming typesafe patches - make stopmachine_timeout from secs to msecs - allow disabling timeout by setting the stopmachine_timeout to 0 Signed-off-by: Hidetoshi Seto <seto.hidetoshi at jp.fujitsu.com> --- include/linux/stop_machine.h | 3 ++ kernel/stop_machine.c | 54 +++++++++++++++++++++++++++++++++++++++-- kernel/sysctl.c | 12 +++++++++ 3 files changed, 66 insertions(+), 3 deletions(-) diff --git a/include/linux/stop_mach...

...uot;( provided we somehow determine that we need ADDS here), then everything else related to ARM instruction generation has been handled in current infrastructure. Is this correct or do we need to modify other things also? 2. In file ARMISelLowering.cpp, inside function FPCCtoARMCC, condition ISD::SETO generates ARMCC::VC ( Overflow clear) condition. Thus, if we are able to appropriately generate ISD::SETO inside SDNode for overflow clear and then map it to ARMCC::VC instruction in IntCCtoARMCC, then will that be enough to generate the an instruction like "addvc"? Thanks Regards, Kapi...

...timize away the cmp instruction by *folding* it in the preceding add when it's legal. Ideally this will be a target independent pass that x86 and other targets can take advantage of as well. > > > 2. In file ARMISelLowering.cpp, inside function FPCCtoARMCC, > condition ISD::SETO generates ARMCC::VC ( Overflow clear) condition. > Thus, if we are able to appropriately generate ISD::SETO inside > SDNode for overflow clear and then map it to ARMCC::VC instruction > in IntCCtoARMCC, then will that be enough to generate the an > instruction like "addvc&q...

On Monday 14 July 2008 21:51:25 Christian Borntraeger wrote: > Am Montag, 14. Juli 2008 schrieb Hidetoshi Seto: > > + /* Wait all others come to life */ > > + while (cpus_weight(prepared_cpus) != num_online_cpus() - 1) { > > + if (time_is_before_jiffies(limit)) > > + goto timeout; > > + cpu_relax(); > > + } > > + > > Hmm. I think this could become interest...

On Monday 14 July 2008 21:51:25 Christian Borntraeger wrote: > Am Montag, 14. Juli 2008 schrieb Hidetoshi Seto: > > + /* Wait all others come to life */ > > + while (cpus_weight(prepared_cpus) != num_online_cpus() - 1) { > > + if (time_is_before_jiffies(limit)) > > + goto timeout; > > + cpu_relax(); > > + } > > + > > Hmm. I think this could become interest...

On 03/14/2017 07:16 AM, vivek pandya wrote: > Hello Hal, > setCondCodeAction(expand) for un ordered comparison generates > semantically wrong code for me for example SETUNE gets converted to > SETOE that causes infinite loops. Can you please explain what is happening? It sounds like a bug we should fix. > > What is ideal place where I can convert unordered comparison to un > comparison + OR + ordered comparison ? > Can I do it by adding required SDNodes ? > for example I am...

...;getInstruction(Inst, Size, *Buffer.take(), 0, llvm::nulls(), llvm::nulls()); // llvm::StringRef TheArchString("arm-apple-darwin"); // std::string normalized = llvm::Triple::normalize(TheArchString); // // llvm::Triple TheTriple; // TheTriple.setArch(llvm::Triple::arm); // TheTriple.setOS(llvm::Triple::Darwin); // TheTriple.setVendor(llvm::Triple::Apple); // llvm::Target *TheTarget = NULL; return 0; }

...t; } > > and code for getFPCCtoXXCC() is as following: > > static void getFPCCtoXXCC(ISD::CondCode CC, XXXCC::CondCodes &CondCode) { > switch (CC) { > default: > llvm_unreachable("Unknown FP condition!"); > case ISD::SETEQ: > case ISD::SETOEQ: > CondCode = XXXCC::COND_E; > break; > case ISD::SETGT: > case ISD::SETOGT: > CondCode = XXXCC::COND_GT; > break; > case ISD::SETGE: > case ISD::SETOGE: > CondCode = XXXCC::COND_GE; > break; > case ISD::SETO...

...:MachO) || StringRef(CPUName).startswith("cortex-m")) { ABIName = "aapcs"; @@ -5128,7 +5128,7 @@ if (Str == "x86_64h") T.setArchName(Str); else if (Str == "armv6m" || Str == "armv7m" || Str == "armv7em") { - T.setOS(llvm::Triple::UnknownOS); + T.setOS(llvm::Triple::NoneOS); T.setObjectFormat(llvm::Triple::MachO); } } Index: test/Driver/macho-embedded.c =================================================================== --- test/Driver/macho-embedded.c (revision 211122) +++ test/Driver/macho-embedd...

On Jul 14, 2008, at 12:59 PM, kapil anand wrote: > Hi all, > > I am using LLVM compiler and CodeGen for generating ARM binaries. > > I was going through the code for ARM backend. I noticed that the ARM > Condition field( Bits 31-28) is generated by converting the > conditions used in icmp and branch. For example, if I have following > C Code > > int a,b,c,d;

...;getInstruction(Inst, Size, *Buffer.take(), 0, llvm::nulls(), llvm::nulls()); // llvm::StringRef TheArchString("arm-apple-darwin"); // std::string normalized = llvm::Triple::normalize(TheArchString); // // llvm::Triple TheTriple; // TheTriple.setArch(llvm::Triple::arm); // TheTriple.setOS(llvm::Triple::Darwin); // TheTriple.setVendor(llvm::Triple::Apple); // llvm::Target *TheTarget = NULL; return 0; } _______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvmd...

Hi all, I am using LLVM compiler and CodeGen for generating ARM binaries. I was going through the code for ARM backend. I noticed that the ARM Condition field( Bits 31-28) is generated by converting the conditions used in icmp and branch. For example, if I have following C Code int a,b,c,d; c = a+b; if(c==0) d = a + 10; Then I get ( Assembly Instructions with opcodes only) add *cmp*