Displaying 7 results from an estimated 7 matches for "setnodeid".
2012 Sep 03
1
[LLVMdev] Selection DAG output as bare DAG, code review
...cks++;
std::cout<<"-We are in Block:"<<numberOfBlocks<<std::endl;
//FIRST OF ALL, LET US TRY NUMBERING THE NODES
int in=0;
for (SelectionDAG::allnodes_iterator I =
CurDAG->allnodes_begin(),E = CurDAG->allnodes_end(); I != E; ++I)
{
I->setNodeId(in++);
}
//END NUMBERING THE NODES.
//LET'S TRY WRITING A FILE
std::ofstream myfile;
std::string filename="DDGBLOCK"+convertInt(numberOfBlocks)+".txt";
myfile.open (filename.c_str());
myfile << "{\n";
for (SelectionDAG::allnod...
2014 Oct 29
2
[LLVMdev] Virtual register def doesn't dominate all uses
...s quite late. With the Option --debug-pass=Structure it's in or after "Assembly Printer".
I do have a very simple DAGToDAGISel::Select() method:
SDNode *MyTargetDAGToDAGISel::Select(SDNode *N)
{
SDLoc dl(N);
// default implementation
if (N -> isMachineOpcode()) {
N -> setNodeId(-1);
return NULL; // Already selected.
}
SDNode *res = SelectCode(N);
return res;
}
Is that too simple? There are no further passes that eliminate anything.
Anyway, I have another test program, that could point to my bug:
int formal_args_3(int p1, int p2, int p3)
{
int v1 = p1;...
2014 Oct 31
2
[LLVMdev] Virtual register def doesn't dominate all uses
...or after "Assembly Printer".
>> I do have a very simple DAGToDAGISel::Select() method:
>>
>> SDNode *MyTargetDAGToDAGISel::Select(SDNode *N)
>> {
>> SDLoc dl(N);
>> // default implementation
>> if (N -> isMachineOpcode()) {
>> N -> setNodeId(-1);
>> return NULL; // Already selected.
>> }
>> SDNode *res = SelectCode(N);
>> return res;
>> }
>>
>> Is that too simple? There are no further passes that eliminate anything.
>>
>> Anyway, I have another test program, that could point t...
2018 Feb 06
0
ConstantFP and Use
...in which case
// this node could become ready. Recompute its flags.
assert(N->getNodeId() != DAGTypeLegalizer::ReadyToProcess &&
N->getNodeId() != DAGTypeLegalizer::Processed &&
"Invalid node ID for RAUW deletion!");
N->setNodeId(DAGTypeLegalizer::NewNode);
NodesToAnalyze.insert(N);
}
First off, I wonder if this assert is actually valid. NodeUpdated is
called for more than node deletion (in fact AFAICT it's called for
everything *but* deletion). The NodeDeleted member right above it has
the exact same asser...
2018 Apr 09
2
Tablegen pattern: How to emit a SDNode in an output pattern?
I'm trying to write a tablegen pattern to that matches a sequence of
SDNodes and emits again an SDNode and another instruction.
The pattern I've written looks like the folowing:
def : Pat<(foo (bar GPR:$rs1), simm12:$imm1),
(bar (BAZ GPR:$rs1, simm12:$imm1))>;
foo and bar are SDNodes, BAZ is an instruction. In particular, bar is
defined as follows:
def bar :
2014 Nov 01
2
[LLVMdev] Virtual register def doesn't dominate all uses
...have a very simple DAGToDAGISel::Select() method:
>>>>
>>>> SDNode *MyTargetDAGToDAGISel::Select(SDNode *N)
>>>> {
>>>> SDLoc dl(N);
>>>> // default implementation
>>>> if (N -> isMachineOpcode()) {
>>>> N -> setNodeId(-1);
>>>> return NULL; // Already selected.
>>>> }
>>>> SDNode *res = SelectCode(N);
>>>> return res;
>>>> }
>>>>
>>>> Is that too simple? There are no further passes that eliminate anything.
>>>>
&g...
2014 Oct 24
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi!
During my backend development I get the error message for some tests:
*** Bad machine code: Virtual register def doesn't dominate all uses. ***
(C source-code, byte-code disassembly and printed machine code at the end of the email)
The first USE of vreg4 in BB#1 has no previous DEF in BB#0 or #1. But why? I can't see how the LLVM byte-code is transformed to the lower machine code.