search for: setmattrs

Displaying 20 results from an estimated 25 matches for "setmattrs".

2015 May 11
4
[LLVMdev] Set up ExecutionEngine according to actual machine capabilities
I am currently setting up my Module with module->setTargetTriple(llvm::sys::getProcessTriple() #ifdef _WIN32 + "-elf" #endif ); And my ExecutionEngine with llvm::EngineBuilder(std::move(module)) .setErrorStr(&err) .setMCPU(llvm::sys::getHostCPUName())
2014 Sep 17
2
[LLVMdev] VEX prefixes for JIT in llvm 3.5
...etc. It's long been on my list of things to investigate anyway as I noticed llvm didn't emit VZEROUPPER calls either, so I supposed it might not be a bad thing to disable vex. That being said, try as I might I can't force avx on (builder.setMCPU("core-avx-i") and/or builder.setMAttrs(vector<string>{"+avx"});). We're still using the old JIT but I just spiked out a move to MCJIT and I still don't see the VEX instructions. Was there a deliberate change on the llvm-side to discourage VEX instructions unless they make a big enough difference (and/or is VZERO...
2013 Nov 12
3
[LLVMdev] Limit loop vectorizer to SSE
On 12 November 2013 16:05, Frank Winter <fwinter at jlab.org> wrote: > engineBuilder.setMCPU(llvm::sys::getHostCPUName()); > Try: engineBuilder.setMAttrs("-avx"); --renato -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131112/4b00aed7/attachment.html>
2014 Sep 17
3
[LLVMdev] VEX prefixes for JIT in llvm 3.5
...estigate anyway as I noticed >> llvm didn't emit VZEROUPPER calls either, so I supposed it might not >> be a bad thing to disable vex. >> >> That being said, try as I might I can't force avx on >> (builder.setMCPU("core-avx-i") and/or >> builder.setMAttrs(vector<string>{"+avx"});). We're still using the old >> JIT but I just spiked out a move to MCJIT and I still don't see the >> VEX instructions. >> >> Was there a deliberate change on the llvm-side to discourage VEX >> instructions unless they m...
2017 May 08
2
LLVM and Xeon Skylake v5
Thank you. I'm letting it auto detect by setting the target using getProcessTarget. I disabled avx512 support by passing -avx512f (and the other variants) to setMAttrs on EngineBuilder. I can see refs to avx512 in X86.td. It's the exact same executable running on Kabylake. What does the Cannot select: specifically mean? Is there some table that doesn't have a definition for a key in it that I would need to patch up? Am I answering your questions? &gt...
2011 Aug 25
2
[LLVMdev] Trouble using the MCJIT: "Target does not support MC emission" error
....setErrorStr(&eeError); >     engineBuilder.setEngineKind(llvm::EngineKind::JIT); >     engineBuilder.setUseMCJIT(true); >     engineBuilder.setMCPU("corei7-avx"); >     std::vector<std::string> attrs; >     attrs.push_back("avx"); >     engineBuilder.setMAttrs(attrs); >     llvm::ExecutionEngine *ee = engineBuilder.create(); > > Note that I have just today filed a bug report also related to jitted > AVX: http://llvm.org/bugs/show_bug.cgi?id=10742 > Thus, it might very well be the case that I am also mistaken and need to > do something d...
2011 Aug 25
0
[LLVMdev] Trouble using the MCJIT: "Target does not support MC emission" error
...ule); engineBuilder.setErrorStr(&eeError); engineBuilder.setEngineKind(llvm::EngineKind::JIT); engineBuilder.setUseMCJIT(true); engineBuilder.setMCPU("corei7-avx"); std::vector<std::string> attrs; attrs.push_back("avx"); engineBuilder.setMAttrs(attrs); llvm::ExecutionEngine *ee = engineBuilder.create(); Note that I have just today filed a bug report also related to jitted AVX: http://llvm.org/bugs/show_bug.cgi?id=10742 Thus, it might very well be the case that I am also mistaken and need to do something different. Best, Ralf Am...
2017 May 08
2
LLVM and Xeon Skylake v5
...arget. > > On 8 May 2017, at 17:55, Andy Schneider via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Thank you. I'm letting it auto detect by setting the target using > getProcessTarget. I disabled avx512 support by passing -avx512f (and the > other variants) to setMAttrs on EngineBuilder. I can see refs to avx512 in > X86.td. It's the exact same executable running on Kabylake. > > What does the Cannot select: specifically mean? Is there some table that > doesn't have a definition for a key in it that I would need to patch up? > > Am I answ...
2011 Sep 09
3
[LLVMdev] runStaticConstructorsDestructors not calling static destructors
...9;m compiling from C++ using Clang, and passing the compiled module to an ExecutionEngine created as follows: EE = llvm::EngineBuilder(globalModule) .setEngineKind(llvm::EngineKind::JIT) .setErrorStr(&err) .setOptLevel(llvm::CodeGenOpt::Default) .setAllocateGVsWithCode(false) //.setMAttrs("-avx") .setMCPU("core2") .create(); EE->DisableLazyCompilation(); After passing in the compiled module, I call: EE->runStaticConstructorsDestructors(module, false); Then to test the tear-down of the module, I call: EE->runStaticConstructorsDestructors(mImpl-&...
2018 Apr 19
1
How to set Target/Triple of ExecutionEngine
...ngineBuilder call selectTarget for you (which is what the no-argument version of EngineBuilder::create does): llvm::ExecutionEngine * ee = builder. setErrorStr( &errStr ). setEngineKind( llvm::EngineKind::JIT ). setTargetOptions( topts ). setMArch(arch). setMAttrs(mattrs). create(); If those are still failing, it would be interesting to get the data layout string that you are getting from the ExecutionEngine instance and compare it to what you are expecting. Cheers, Lang. On Thu, Apr 19, 2018 at 1:56 AM, edA-qa mort-ora-y via llvm-dev < llvm-de...
2011 Aug 26
0
[LLVMdev] Trouble using the MCJIT: "Target does not support MC emission" error
...;> engineBuilder.setEngineKind(llvm::EngineKind::JIT); >> engineBuilder.setUseMCJIT(true); >> engineBuilder.setMCPU("corei7-avx"); >> std::vector<std::string> attrs; >> attrs.push_back("avx"); >> engineBuilder.setMAttrs(attrs); >> llvm::ExecutionEngine *ee = engineBuilder.create(); >> >> Note that I have just today filed a bug report also related to jitted >> AVX: http://llvm.org/bugs/show_bug.cgi?id=10742 >> Thus, it might very well be the case that I am also mistaken and need t...
2014 Sep 17
2
[LLVMdev] VEX prefixes for JIT in llvm 3.5
...dn't emit VZEROUPPER calls either, so I supposed it might not >> >> be a bad thing to disable vex. >> >> >> >> That being said, try as I might I can't force avx on >> >> (builder.setMCPU("core-avx-i") and/or >> >> builder.setMAttrs(vector<string>{"+avx"});). We're still using the old >> >> JIT but I just spiked out a move to MCJIT and I still don't see the >> >> VEX instructions. >> >> >> >> Was there a deliberate change on the llvm-side to discourage VEX...
2011 Aug 25
3
[LLVMdev] Trouble using the MCJIT: "Target does not support MC emission" error
I'm trying to wire up some code to use the MC-based JIT; my understanding is that it should be able to JIT AVX code (and that the regular JIT cannot). However, I'm getting the error "Target does not support MC emission!" when I call EngineBuilder::create(). I assume that I'm just not doing something necessary for initialization, but I'm not sure what it would be--I am
2011 Sep 09
0
[LLVMdev] runStaticConstructorsDestructors not calling static destructors
...ineBuilder(globalModule) >                        .setEngineKind(llvm::EngineKind::JIT) >                        .setErrorStr(&err) >                        .setOptLevel(llvm::CodeGenOpt::Default) >                        .setAllocateGVsWithCode(false) >                        //.setMAttrs("-avx") >                        .setMCPU("core2") >                        .create(); > EE->DisableLazyCompilation(); > > After passing in the compiled module, I call: > > EE->runStaticConstructorsDestructors(module, false); > > Then to test the...
2011 Aug 26
2
[LLVMdev] Trouble using the MCJIT: "Target does not support MC emission" error
...neBuilder.setEngineKind(llvm::EngineKind::JIT); >>> engineBuilder.setUseMCJIT(true); >>> engineBuilder.setMCPU("corei7-avx"); >>> std::vector<std::string> attrs; >>> attrs.push_back("avx"); >>> engineBuilder.setMAttrs(attrs); >>> llvm::ExecutionEngine *ee = engineBuilder.create(); >>> >>> Note that I have just today filed a bug report also related to jitted >>> AVX: http://llvm.org/bugs/show_bug.cgi?id=10742 >>> Thus, it might very well be the case that I am also...
2014 Sep 18
5
[LLVMdev] VEX prefixes for JIT in llvm 3.5
...er, so I supposed it might not >>>>>> be a bad thing to disable vex. >>>>>> >>>>>> That being said, try as I might I can't force avx on >>>>>> (builder.setMCPU("core-avx-i") and/or >>>>>> builder.setMAttrs(vector<string>{"+avx"});). We're still using the >>>>>> old >>>>>> JIT but I just spiked out a move to MCJIT and I still don't see the >>>>>> VEX instructions. >>>>>> >>>>>> Was there a...
2010 Mar 18
1
[LLVMdev] Turning on/off sub-target features (e.g. Altivec on PowerPC)
Hello, I'm using Mono with experimental LLVM backend support on PowerPC. I noticed that although LLVM's IR contains SIMD instructions the assembly produced doesn't contain any Altivec instructions and my PowerPC970 machine of course has Altivec support. Isn't there some kind of autodetection? I searched in Target sources but only found out that Altivec is disabled by default. Can
2013 Nov 12
2
[LLVMdev] Limit loop vectorizer to SSE
On 12 November 2013 15:53, Frank Winter <fwinter at jlab.org> wrote: > .. forcing the vector size to 4 does not prevent using AVX. > Sure. That's more for tests than anything else. So, there are ways of disabling stuf in Clang, for instance "-mattr=-avx" or "-target-feature -avx", but I'm not sure how you're doing it in the JIT. I'm also not sure
2013 Nov 12
0
[LLVMdev] Limit loop vectorizer to SSE
On 12/11/13 11:01, Renato Golin wrote: > On 12 November 2013 15:53, Frank Winter <fwinter at jlab.org > <mailto:fwinter at jlab.org>> wrote: > > .. forcing the vector size to 4 does not prevent using AVX. > > > Sure. That's more for tests than anything else. > > So, there are ways of disabling stuf in Clang, for instance > "-mattr=-avx"
2010 Mar 18
1
[LLVMdev] Turning sub-target features on/off (e.g. Altivec on PowerPC)
Hello, I'm using Mono with experimental LLVM backend support on PowerPC. I noticed that although LLVM's IR contains SIMD instructions the assembly produced doesn't contain any Altivec instructions and my PowerPC970 machine of course has Altivec support. Isn't there some kind of autodetection? I searched in Target sources but only found out that Altivec is disabled by default. Can