Displaying 6 results from an estimated 6 matches for "setmachineoperandreg".
2005 Sep 07
4
[LLVMdev] LiveIntervals, replace register with representative register?
...eOperand& mop = mii->getOperand(i);
if (mop.isRegister() && mop.getReg() &&
MRegisterInfo::isVirtualRegister(mop.getReg())) {
// replace register with representative register
unsigned reg = rep(mop.getReg());
mii->SetMachineOperandReg(i, reg);
LiveInterval &RegInt = getInterval(reg);
RegInt.weight +=
(mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
--
Tzu-Chien Chiu,
3D Graphics Hardware Architect
<URL:http://www.csie.nctu.edu.tw/~jwchiu>
2006 Apr 29
2
[LLVMdev] Register allocation in LLVM
...ter allocation:
- To send registers to memory:
RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
- To bring registers from memory:
RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
- Given instruction i, virtual v, and machine reg m, allocate m to v at i:
MI->SetMachineOperandReg(i, physReg);
And PHI deconstruction:
- to remove instructions from Basic Blocks:
MachineInstr *MPhi = MBB.remove(MBB.begin());
delete MPhi;
- to create new instructions:
BuildMI, http://llvm.org/docs/CodeGenerator.html
- to discover the origin block of each operand in the phi functi...
2006 May 01
0
[LLVMdev] Register allocation in LLVM
...end registers to memory:
> RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
> - To bring registers from memory:
> RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
> - Given instruction i, virtual v, and machine reg m, allocate m to v at i:
> MI->SetMachineOperandReg(i, physReg);
> And PHI deconstruction:
>
> - to remove instructions from Basic Blocks:
> MachineInstr *MPhi = MBB.remove(MBB.begin());
> delete MPhi;
>
> - to create new instructions:
> BuildMI, http://llvm.org/docs/CodeGenerator.html
>
> - to discover the ori...
2005 Sep 07
0
[LLVMdev] LiveIntervals, replace register with representative register?
...mii->getOperand(i);
> if (mop.isRegister() && mop.getReg() &&
> MRegisterInfo::isVirtualRegister(mop.getReg())) {
> // replace register with representative register
> unsigned reg = rep(mop.getReg());
> mii->SetMachineOperandReg(i, reg);
>
> LiveInterval &RegInt = getInterval(reg);
> RegInt.weight +=
> (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
>
>
-Chris
--
http://nondot.org/sabre/
http://llvm.org/
2005 Sep 07
0
[LLVMdev] LiveIntervals, replace register with representative register?
...gt;getOperand(i);
> if (mop.isRegister() && mop.getReg() &&
> MRegisterInfo::isVirtualRegister(mop.getReg())) {
> // replace register with representative register
> unsigned reg = rep(mop.getReg());
> mii->SetMachineOperandReg(i, reg);
>
> LiveInterval &RegInt = getInterval(reg);
> RegInt.weight +=
> (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth);
>
After joining intervals some moves are unecessary. If for example this
instruction was in the code:
mov...
2006 May 01
2
[LLVMdev] Register allocation in LLVM
...t; RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
>> - To bring registers from memory:
>> RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
>> - Given instruction i, virtual v, and machine reg m, allocate m to
>> v at i:
>> MI->SetMachineOperandReg(i, physReg);
>> And PHI deconstruction:
>>
>> - to remove instructions from Basic Blocks:
>> MachineInstr *MPhi = MBB.remove(MBB.begin());
>> delete MPhi;
>>
>> - to create new instructions:
>> BuildMI, http://llvm.org/docs/CodeGenerator.html...