search for: setloadxact

Displaying 5 results from an estimated 5 matches for "setloadxact".

2009 Feb 19
2
[LLVMdev] Possible error in LegalizeDAG
...blocking issue that I just > cannot seem to resolve without modifying the LLVM codebase to remove the > extend + load -> extload combining step. >LLVM will "uncombine" it for you if you use setLoadExtAction with the >appropriate arguments. >-Eli I've tried setting setLoadXAction to Custom, Legal, Expand and Promote. I assert somewhere when I try to custom expanding this operation because it expects it to be a certain form, but my custom load instruction has a different form. Setting it to Legal generates the sext_load in the first dag combine pass, because it never chec...
2009 Feb 19
0
[LLVMdev] Possible error in LegalizeDAG
..., however the hardware only supports natively 32bit aligned > loads, therefore I have to read in 4 i8's and unpack them and shift them > based on the read address. So any i8 load has a 75% chance of being > unaligned on my hardware, Oh, okay, makes sense. > I've tried setting setLoadXAction to Custom, Legal, Expand and Promote. > Setting it to Expand does not expand it to > sign_extend and load but to extload and sign_extend, but I don't > support extload either. I suppose you could consider that a bug. That said, why is this difficult to implement? You can just tr...
2009 Feb 18
0
[LLVMdev] Possible error in LegalizeDAG
On Wed, Feb 18, 2009 at 10:14 AM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > I'm still trying to track down some alignment issues with loads(i.e. 8/16 > bit loads being turned into 32bit sign extending loads) and I cannot for the > life of me seem to figure out how to enter this section of code: > > // If this is an unaligned load and the target doesn't support
2009 Feb 18
2
[LLVMdev] Possible error in LegalizeDAG
I'm still trying to track down some alignment issues with loads(i.e. 8/16 bit loads being turned into 32bit sign extending loads) and I cannot for the life of me seem to figure out how to enter this section of code: // If this is an unaligned load and the target doesn't support it, // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned
2008 Oct 06
1
[LLVMdev] sign extensions on loads?
I have a simple test case that my code generator handles fine when using optimizations, but when I disable optimizations, It turns into a sequence of instructions that I can't figure out what to setup to get it to generate the correct code. The instructions in question are: %tmp1 = load float* %test ; <float> [#uses=1] %conv = fpext float %tmp1 to double ;