Displaying 7 results from an estimated 7 matches for "setiskill".
2009 Jul 17
2
[LLVMdev] Bug in LiveIntervals? Please Examine
...gt;createVirtualRegister(RC);
MachineInstrBuilder MIB =
BuildMI(*RMBB, RMI, RMI->getDebugLoc(),
tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg);
(*MIB).getOperand(0).setIsUndef();
RMO.setReg(NewVReg);
RMO.setIsUndef();
RMO.setIsKill();
}
Souldn't there be a call to vrm.grow() after each call to
mri->createVirtualRegister()?
-Dave
2009 Jul 17
0
[LLVMdev] Bug in LiveIntervals? Please Examine
...;
> MachineInstrBuilder MIB =
> BuildMI(*RMBB, RMI, RMI->getDebugLoc(),
> tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg);
> (*MIB).getOperand(0).setIsUndef();
> RMO.setReg(NewVReg);
> RMO.setIsUndef();
> RMO.setIsKill();
> }
>
> Souldn't there be a call to vrm.grow() after each call to
> mri->createVirtualRegister()?
No. This function is run during the analysis stage. vrm is actually
owned by the register allocator which then passed it into
liveintervals. Is there an actual problem t...
2017 Jun 27
4
Ok with mismatch between dead-markings in BUNDLE and bundled instructions?
...uction operands.
bool hasLiveDef = false;
for (const auto &OpPair : Ops) {
MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
MO.setReg(NewVReg);
if (MO.isUse()) {
if (!OpPair.first->isRegTiedToDefOperand(OpPair.second))
MO.setIsKill();
} else {
if (!MO.isDead())
hasLiveDef = true;
}
So I suppose we could either make LiveIntervals::computeDeadValues mark
the individual defs dead as well, or we could change
InlineSpiller::spillAroundUses so that if we only look at the BUNDLE
instruction (if...
2011 Oct 12
1
[LLVMdev] Problem in TwoAddressInstructionPass::runOnMachineFunction regarding subRegs
...stanceMap.
DistanceMap.insert(std::make_pair(prevMI, Dist));
@@ -1190,11 +1198,13 @@ bool
TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
"inconsistent operand info for 2-reg pass");
if (MO.isKill()) {
MO.setIsKill(false);
RemovedKillFlag = true;
}
+ unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
MO.setReg(regA);
+ MO.setSubReg(regASubIdx);
}
/Mikael Holmén
2017 Jun 29
2
Ok with mismatch between dead-markings in BUNDLE and bundled instructions?
> On Jun 28, 2017, at 5:10 PM, Quentin Colombet via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> Oh wait, vreg1 is indeed used.
> Yeah, having a dead flag here sounds wrong.
I mean on the instruction itself.
On the bundle, that’s debatable. That would fit the semantic “if no side effect you can kill it” (here there is side effect, we define other vregs).
>
>> On
2017 Aug 22
5
[RFC] mir-canon: A new tool for canonicalizing MIR for cleaner diffing.
Patch for review.
On Mon, Aug 21, 2017 at 11:45 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com>
wrote:
> Ping.
>
> Still working on preparing code for review. Will have a patch for review
> ready in the coming days.
>
> PL
>
> On Tue, Aug 15, 2017 at 12:06 PM Puyan Lotfi <puyan.lotfi.llvm at gmail.com>
> wrote:
>
>> Hi,
>>
>>
>>
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
Hi,
I'm lowering some of the logical operators (by example the | operator) on integer32.
Sadly my target only provide native instruction on high and low parts of 32 bits registers.
So, I have to generate a sequence of two native instructions (LOR followed by HOR).
I've introduced an Pseudo instruction with a custom inserter.
def OR_A_oo : CLPPseudoInst<(ins