Displaying 6 results from an estimated 6 matches for "setisdef".
2018 Mar 29
4
Mapping virtual registers to physical registers
...destination = MI->getOperand(0);
MachineOperand offset = MI->getOperand(1);
unsigned destinationReg = destination.getReg();
int64_t FrameIndex = offset.getIndex();
destination.setReg(CLP::FA_ROFF0+FrameIndex);
destination.setIsDef(true);
TII->loadRegFromStackSlot(*MBB,
MI, destinationReg, FrameIndex,
&CLP::FPUaOffsetClassRegClass, TRI);
The code after customInserter seems valid but the compilation later ha...
2018 Apr 02
0
Mapping virtual registers to physical registers
...nged made by
calling setReg will be discarded one you go out of scope. Having said
that, setReg can be used to change the register in the given operand.
Make sure to change the subregister to 0, since physical registers are
not allowed to have explicit subregisters in machine operands. Calling
setIsDef on an existing operand is not a good practice. If you want to
make significant changes to an instruction, it's usually better to build
a new one and remove the old one.
Hope this helps,
-Krzysztof
On 3/29/2018 8:47 AM, Dominique Torette via llvm-dev wrote:
> Hi,
>
> In the context...
2018 Apr 03
1
Mapping virtual registers to physical registers
...changed made by calling setReg will be discarded one you go out of scope. Having said that, setReg can be used to change the register in the given operand.
Make sure to change the subregister to 0, since physical registers are not allowed to have explicit subregisters in machine operands. Calling setIsDef on an existing operand is not a good practice. If you want to make significant changes to an instruction, it's usually better to build a new one and remove the old one.
Hope this helps,
-Krzysztof
On 3/29/2018 8:47 AM, Dominique Torette via llvm-dev wrote:
> Hi,
>
> In the context o...
2018 Mar 30
0
Mapping virtual registers to physical registers
...destination = MI->getOperand(0);
MachineOperand offset = MI->getOperand(1);
unsigned destinationReg = destination.getReg();
int64_t FrameIndex = offset.getIndex();
destination.setReg(CLP::FA_ROFF0+FrameIndex);
destination.setIsDef(true);
TII->loadRegFromStackSlot(*MBB,
MI, destinationReg, FrameIndex,
&CLP::FPUaOffsetClassRegClass, TRI);
The code after customInserter seems valid but the compilation later ha...
2011 Feb 18
0
[LLVMdev] Adding "S" suffixed ARM/Thumb2 instructions
On Feb 17, 2011, at 10:35 PM, Вадим Марковцев wrote:
> Hello everyone,
>
> I've added the "S" suffixed versions of ARM and Thumb2 instructions to tablegen. Those are, for example, "movs" or "muls".
> Of course, some instructions have already had their twins, such as add/adds, and I leaved them untouched.
Adding separate "s" instructions is
2011 Feb 18
2
[LLVMdev] Adding "S" suffixed ARM/Thumb2 instructions
Hello everyone,
I've added the "S" suffixed versions of ARM and Thumb2 instructions to
tablegen. Those are, for example, "movs" or "muls".
Of course, some instructions have already had their twins, such as add/adds,
and I leaved them untouched.
Besides, I propose the codegen optimization based on them, which removes the
redundant comparison in patterns like
orr