search for: setindexedstoreact

...nc load and store's. setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); Then the DAGCombiner calls into the backe...

Hi Steve, Thanks for the tip regarding MIOperandInfo, I didn't think of that part of the tablegen description. Sadly, I did actually mean: r1 = *(i0 += m0). So increment i0 by m0. Read memory the memory location "pointed" to by i0. Store in r1. Sadly I am not too familiar with compiler terminology, so I don't know if there is a proper term for such a load. On Thu, Oct 23,

...ode the information that the pointer is incremented? As you seem to be aware, LLVM has patterns specifically to match pre/post increment loads and stores (post_store). In your *ISelLowering.cpp file, you'll need to call setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same for setIndexedStoreAction. Then you'll need to implement a getPostIndexedAddressParts function in that same file (you can look in the ARM backend for an example). If you can select your indirect moves using TableGen patterns, then you can probably use the post_store pattern. -Hal > > Thanks and regards, &gt...

Hi, We have an architecture where the indirect move instruction implicitly increments the pointer value after the move. We have Instruction format and pattern for this type of instructions. How to encode the information that the pointer is incremented? Thanks and regards, Shashidhar

...the information that the pointer is incremented? > As you seem to be aware, LLVM has patterns specifically to match pre/post increment loads and stores (post_store). In your *ISelLowering.cpp file, you'll need to call setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same for setIndexedStoreAction. Then you'll need to implement a getPostIndexedAddressParts function in that same file (you can look in the ARM backend for an example). If you can select your indirect moves using TableGen patterns, then you can probably use the post_store pattern. > > -Hal > >> Thanks and...

Hi, I'm trying to enable the pre-decrementing and post-incrementing based addressing modes for my target. So far without any success :( I enabled these modes in my TargetLowering class using setIndexedLoadAction and setIndexedStoreAction calls. I also defined getPreIndexedAddressParts and getPostIndexedAddressParts. And I can see that DAGCombiner::CombineToPostIndexedLoadStore is invoked. But this function never does any replacements and very seldomly invoke getPostIndexedAddressParts and so on, even in those situations where I...

Hi Chris, --- Chris Lattner <sabre at nondot.org> wrote: > On Wed, 29 Nov 2006, Roman Levenstein wrote: > > Thanks, this is a good idea. > > > > But I cannot figure out how to make a machine function pass run > > _BEFORE_ the RA. I guess I'm missing something very obvious. > > In your target's TargetMachine::addInstSelector method, add it to the

...ed? > > As you seem to be aware, LLVM has patterns specifically to match > > pre/post increment loads and stores (post_store). In your > > *ISelLowering.cpp file, you'll need to call > > setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same > > for setIndexedStoreAction. Then you'll need to implement a > > getPostIndexedAddressParts function in that same file (you can > > look in the ARM backend for an example). If you can select your > > indirect moves using TableGen patterns, then you can probably use > > the post_store pattern. &g...

...; As you seem to be aware, LLVM has patterns specifically to match >>> pre/post increment loads and stores (post_store). In your >>> *ISelLowering.cpp file, you'll need to call >>> setIndexedLoadAction(ISD::POST_INC, <type>, Legal), and the same >>> for setIndexedStoreAction. Then you'll need to implement a >>> getPostIndexedAddressParts function in that same file (you can >>> look in the ARM backend for an example). If you can select your >>> indirect moves using TableGen patterns, then you can probably use >>> the post_store...

I have a rudimentary implementation for load and store instructions, where the memory address operand is automatically post-incremented when the load or store instruction is issued. However, this is currently coded using custom lowering, and explicit pattern matching in the 'ISelDAGtoDAG' implementation. But it seems to me that I ought to be able to achieve this exclusively using

...m I guess I should do something like: - // Inspired from ARMISelLowering.cpp: for (unsigned im = (unsigned)ISD::PRE_INC; im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { setIndexedLoadAction(im, MVT::i64, Legal); setIndexedLoadAction(im, MVT::i16, Promote); setIndexedStoreAction(im, MVT::i64, Legal); setIndexedStoreAction(im, MVT::i16, Promote); } - do custom instruction selection for masked_gather and masked_scatter . Best regards, Alex On 12/12/2016 4:18 AM, Alex Susu wrote: > Hello. > I wanted to inform that I fixed the bug fro...

Hello. I wanted to inform that I fixed the bug from the previous email. The main reason for the bug was that I thought that the SDNode masked_gather is returning only 1 value, but it returns 2 (hence, I guess, the earlier reported, difficult to follow, error: "Assertion `New->getNumTypes() == 1"). masked_gather returns 2 values because: // SDTypeProfile -

...address modes I’ve implemented something similar, though maybe not similar enough to be able to help you. My target supports increment and decrement, both pre and post, by an explicit constant in the range 1 to 8. I didn’t write any custom lowering code, just used setIndexedLoadAction() and setIndexedStoreAction() in my ISelLowering to identify the types and actions, e.g. setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); I didn’t think it was possible to match an indexed load or store using a TableGen pattern because it can’t match instructions with more than one output operand, t...