search for: setge

...ral this can often lead to better code (and it does for Mips 16 for sure), except at the boundary condition where k==-32768 Then it creates the literal -32769 which cannot be placed in a simple immediate field. That creates a lot of extra code for Mips 16. I had originally written a pattern for setge when the right operand is a constant. def: Mips16Pat <(setge CPU16Regs:$lhs, immZExt16:$rhs), (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), (LiRxImmX16 1))>; I was able to work around this boundary case by doing the reverse transformation at the boundary. i..e....

Hi LLVM, clang, I'm trying to write a portable version of __builtin_add_overflow() it a way that the compiler would recognize the pattern and use the add_overflow intrinsic / the best possible machine instruction. Here are docs about these builtins: https://clang.llvm.org/docs/LanguageExtensions.html#checked-arithmetic-builtins . With unsigned types this is easy: int uaddo_native(unsigned

what's the semantics for setCC if one of the operands is NULL pointer? %ptr=alloc int seteq int*, %pt, NULL what's the result for the second instruction? How about setne, setlt, setgt, setle, and setge? Thanks! Jianzhong

...)], s_br>; Tablegen reports: BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2, SETEQ:Other), (bb:Other):$SImm16) as soon as I add a register class that supports either [v2i32] or [v4i32] I get the following: BGE: (brcond:void (setcc:isInt GPRegs:i32:$Rsrc1, 0:i32, SETGE:Other), (bb:Other):$SImm16) build/llvm/trunk/Debug/bin/tblgen: In BGE: Could not infer all types in pattern! Thanks -- Christopher Lamb

Before I file a bug, I thought I'd check to make sure something hasn't changed. Stacker used to work in 1.2, now it fails on six tests. All six tests pertain to use of the SetLT, SetGT, SetLE, and SetGE SetCondInst. In my test programs they all fail, regardless of the values. The *only* thing I've done to Stacker is to change the base type involved in the comparison from int to long. Is there something "different" about the comparison of longs? The code generated by Stacker Compile...

On Sun, 9 May 2004, Reid Spencer wrote: > Before I file a bug, I thought I'd check to make sure something hasn't > changed. Stacker used to work in 1.2, now it fails on six tests. All six > tests pertain to use of the SetLT, SetGT, SetLE, and SetGE SetCondInst. > In my test programs they all fail, regardless of the values. > > The *only* thing I've done to Stacker is to change the base type > involved in the comparison from int to long. Is there something > "different" about the comparison of longs? > > The...

Compile with -O3 -m32 (see <https://godbolt.org/z/yCpBpM>): long lsign(long x) { return (x > 0) - (x < 0); } long long llsign(long long x) { return (x > 0) - (x < 0); } While the code generated for the "long" version of this function is quite OK, the code for the "long long" version misses an obvious optimisation: lsign: # @lsign mov

...> BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2, > SETEQ:Other), (bb:Other):$SImm16) > > as soon as I add a register class that supports either [v2i32] or > [v4i32] I get the following: > > BGE: (brcond:void (setcc:isInt GPRegs:i32:$Rsrc1, 0:i32, > SETGE:Other), (bb:Other):$SImm16) > build/llvm/trunk/Debug/bin/tblgen: In BGE: Could not infer all types > in pattern! Comparison nodes don't support vector types. -Chris -- http://nondot.org/sabre/ http://llvm.org/

Chris Lattner wrote: > The way to deal with this is to add LLVM intrinsics, but only for > functions that set errno. For example, you could add llvm.sqrt, which > is just undefined on a negative value other than -0.0. For your uses, > you just emit llvm.sqrt, the C frontend will make use of it and wrap > errno handling around it as required. > > For functions like

Hi, The attached patch implements sub.ovf/mul.ovf intrinsics similarly to the recently added add.ovf intrinsics. These are useful for implementing some vm instructions like sub.ovf/mul.ovf in .NET IL efficiently. sub.ovf is supported in target independent lowering and on x86, while mul.ovf is only supported in the x86 backend. Please review

...def : MipsPat<(i32 immSExt16:$in), (ADDiu ZERO, imm:$in)>; def : MipsPat<(i32 immZExt16:$in), (ORi ZERO, imm:$in)>; def : MipsPat<(i32 immLow16Zero:$in), (LUi (HI16 imm:$in))>; Here are some which have several instructions multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { def : MipsPat<(setge RC:$lhs, RC:$rhs), (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; def : MipsPat<(setuge RC:$lhs, RC:$rhs), (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; } On 07/20/2012 07:...

...des &CondCode) { switch (CC) { default: llvm_unreachable("Unknown FP condition!"); case ISD::SETEQ: case ISD::SETOEQ: CondCode = XXXCC::COND_E; break; case ISD::SETGT: case ISD::SETOGT: CondCode = XXXCC::COND_GT; break; case ISD::SETGE: case ISD::SETOGE: CondCode = XXXCC::COND_GE; break; case ISD::SETOLT: case ISD::SETLT: CondCode = XXXCC::COND_LT; break; case ISD::SETOLE: case ISD::SETLE: CondCode = XXXCC::COND_LE; break; case ISD::SETONE: case ISD::SETNE: Con...

Thanks for your reply. We are trying to implement a simple Mips-based CPU with just for teaching purpose, so we delete some instructions which are not commonly used, thus the task won't be too hard for students. I am responsible for modifying the compiler so that the compiler won't emit unsupported instructions. In order to avoid "can not select" error, I am trying to expand

...> llvm_unreachable("Unknown FP condition!"); > case ISD::SETEQ: > case ISD::SETOEQ: > CondCode = XXXCC::COND_E; > break; > case ISD::SETGT: > case ISD::SETOGT: > CondCode = XXXCC::COND_GT; > break; > case ISD::SETGE: > case ISD::SETOGE: > CondCode = XXXCC::COND_GE; > break; > case ISD::SETOLT: > case ISD::SETLT: > CondCode = XXXCC::COND_LT; > break; > case ISD::SETOLE: > case ISD::SETLE: > CondCode = XXXCC::COND_LE; > brea...

...[1]* * Value |= op & UINT64_C(65535);* * break;* * }* I have added different encoder method for operand(1) but that operand is not even propagated in Encodeinstruction.. by the way,this is how I have defined BGEID.. *def : Pat<(brcond (setcc (i32 GR32:$L), (i32 GR32:$R), SETGE), bb:$T),* * (BGEID (CMP GR32:$L, GR32:$R), bb:$T)>;* *def BGEID : TBT<0b101110, (outs), (ins GR32:$ra, brtarget:$offset), "bgeid\t$ra,$offset", [], IIC_BRc> {* * let rd = 0b10101;* *}* I don't know where I am doing wrong.please provide your notes... Thank...

Hi, I have added Branch condition BGEID like below… *def : Pat<(brcond (setcc (i32 GR32:$L), (i32 GR32:$R), SETGE), bb:$T),* * (BGEID (CMP GR32:$L, GR32:$R), bb:$T)>;* *def BGEID : TBT<0b101110, (outs), (ins GR32:$ra, brtarget:$offset), "bgeid\t$ra,$offset", [], IIC_BRc> {* * let rd = 0b10101;* *}* *def brtarget : Operand<OtherVT>* *{* * let PrintMethod = &q...

...L is zero and alloca returns an unsigned nonzero pointer value. > what's the semantics for setCC if one of the operands is NULL pointer? > %ptr=alloc int > seteq int*, %pt, NULL > > what's the result for the second instruction? How about setne, setlt, > setgt, setle, and setge? Thanks! > > Jianzhong > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://mail.cs.uiuc.edu/mailman/listinfo/llvmdev -- gaeke at uiuc.edu

...setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2, >> SETEQ:Other), (bb:Other):$SImm16) >> >> as soon as I add a register class that supports either [v2i32] or >> [v4i32] I get the following: >> >> BGE: (brcond:void (setcc:isInt GPRegs:i32:$Rsrc1, 0:i32, >> SETGE:Other), (bb:Other):$SImm16) >> build/llvm/trunk/Debug/bin/tblgen: In BGE: Could not infer all types >> in pattern! > > Comparison nodes don't support vector types. Then this node would really benefit from a type constraint that indicates this. Here the type constraint '...

...t; case ISD::SETOEQ: >> CondCode = XXXCC::COND_E; >> break; >> case ISD::SETGT: >> case ISD::SETOGT: >> CondCode = XXXCC::COND_GT; >> break; >> case ISD::SETGE: >> case ISD::SETOGE: >> CondCode = XXXCC::COND_GE; >> break; >> case ISD::SETOLT: >> case ISD::SETLT: >> CondCode = XXXCC::COND_LT; >> break; >> c...

...BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32: > $Rsrc2, SETEQ:Other), (bb:Other):$SImm16) > > as soon as I add a register class that supports either [v2i32] or > [v4i32] I get the following: > > BGE: (brcond:void (setcc:isInt GPRegs:i32:$Rsrc1, 0:i32, > SETGE:Other), (bb:Other):$SImm16) > build/llvm/trunk/Debug/bin/tblgen: In BGE: Could not infer all > types in pattern! > > Thanks > -- > Christopher Lamb