search for: seteq

>> Is there a pass that will transform this: >> %cc = seteq ushort %val, 0 >> >> into this: >> %cc = cast ushort %val to bool >> >> Would instcombine be the logical place to do this? >> >> In my situation, this bool value feeds a select instruction. Because >> casting inverts the condition, the select would...

Is there a pass that will transform this: %cc = seteq ushort %val, 0 into this: %cc = cast ushort %val to bool Would instcombine be the logical place to do this? Thanks.

On Thu, May 19, 2005 at 03:27:02PM -0500, Eric Zimmerman wrote: > Is there a pass that will transform this: > %cc = seteq ushort %val, 0 > > into this: > %cc = cast ushort %val to bool > > Would instcombine be the logical place to do this? In my situation, this bool value feeds a select instruction. Because casting inverts the condition, the select would have to switch the operands, but I th...

...fine (clear-tag x) (bit-shl (bit-shr x 2) 2)) (llvm-define (get-tag x) (bit-and x 3)) (llvm-define (make-pointer x) (bit-or (clear-tag x) 1)) (llvm-define (make-function-pointer x) (bit-or (clear-tag x) 3)) (llvm-define (points-to x) (clear-tag x)) (llvm-define (number? x) (seteq (get-tag x) 0)) (llvm-define (vector? x) (seteq (get-tag x) 1)) (llvm-define (procedure? x) (seteq (get-tag x) 3)) (llvm-define (make-vector raw-size) (make-pointer (cast "uint*" (store raw-size (malloc (add raw-size 1))) "uint&quo...

what's the semantics for setCC if one of the operands is NULL pointer? %ptr=alloc int seteq int*, %pt, NULL what's the result for the second instruction? How about setne, setlt, setgt, setle, and setge? Thanks! Jianzhong

..., 0x170e360 [ID=17] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170e860: i16 = Register %reg16386 [ID=7] 0x170e360: i16,ch = CopyFromReg 0x16d5748, 0x170e260 [ID=14] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170e260: i16 = Register %reg16390 [ID=4] 0x170ed00: ch = seteq [ORD=1] [ID=9] 0x170dc60: i16,ch = CopyFromReg 0x16d5748, 0x170db60 [ORD=1] [ID=11] 0x16d5748: ch = EntryToken [ORD=1] [ID=0] 0x170db60: i16 = Register %reg16387 [ORD=1] [ID=1] 0x170ec00: i16 = Constant<0> [ORD=1] [ID=8] 0x170ef00: ch = BasicBlock<bb1 0x170a5d8> [ID=10] In...

...ll. It seems to affect a smattering of node types. Any insights? For instance: where GPRegs contains types [i32, f32] def BEQ : IF8<Opc.BEQ, (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), "beq $Rsrc1, $Rsrc2, $SImm16", [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: $SImm16)], s_br>; Tablegen reports: BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2, SETEQ:Other), (bb:Other):$SImm16) as soon as I add a register class that supports either [v2i32] or [v4i32] I get the following: BGE: (brcond:v...

...} else if(GetElementPtrInst *GEPI= dyn_cast<GetElementPtrInst>(j)) { ValueList.push_back(GEPI); }; }; To find the first instructions which are not depending on others results. So far it seems to be working but i am missing instructions like: %tmp.1 = seteq int %argc, 2 ; <bool> [#uses=1] There seems only an function like llvm::Instruction::mayWriteToMemory but nothing like llvm::Instruction::mayReadFromMemory or s.t. with similiar functionality? Or else: if there is an even easier way to get the non data depending instruction fr...

On Sat, 17 Jul 2004, Chris Lattner wrote: > > http://www.ida.liu.se/~tobnu/scheme2llvm/ > > Looks great! > > > (what's a blurb? :) > > Just a summary, so that I can add an entry to this page: > http://llvm.cs.uiuc.edu/ProjectsWithLLVM/ Maybe this for now: "This is a small self applicable scheme compiler for LLVM. The code is quite similar to the code in

On Fri, 12 May 2006, Silken Tiger wrote: > To find the first instructions which are not depending on others results. So > far it seems to be working but i am missing instructions like: > %tmp.1 = seteq int %argc, 2 ; <bool> [#uses=1] > There seems only an function like llvm::Instruction::mayWriteToMemory > but nothing like llvm::Instruction::mayReadFromMemory or s.t. with similiar > functionality? > > Or else: if there is an even easier way to get the non data dep...

...e types. Any > insights? > > For instance: > > where GPRegs contains types [i32, f32] > > def BEQ : IF8<Opc.BEQ, > (ops GPRegs:$Rsrc1, GPRegs:$Rsrc2, brtarget:$SImm16), > "beq $Rsrc1, $Rsrc2, $SImm16", > [(brcond (i32 (seteq GPRegs:$Rsrc1, GPRegs:$Rsrc2)), bb: > $SImm16)], s_br>; > > Tablegen reports: > BEQ: (brcond:void (setcc:i32 GPRegs:i32:$Rsrc1, GPRegs:i32:$Rsrc2, > SETEQ:Other), (bb:Other):$SImm16) > > as soon as I add a register class that supports either [v2i32] or > [v4i32] I get...

...9/04. > This causes some problems for architectures that use conditional moves > to implement select (alpha and ARM). For example, on 2006/09/03 a "if > (a) return 0; else return 1;" compiled to This is not because of how it handles select. For example: int %foo(int %x) { %b = seteq int %x, 5 %r = select bool %b, int 3, int 7 ret int %r } int %bar(int %x) { %b = seteq int %x, 5 br bool %b, label %t, label %f t: ret int 1 f: ret int 2 } compiles to: foo: lda $0,3($31) zapnot $16,15,$1 cmpeq $1,5,$1 cmoveq $1,7,$0 ret $31,($26),1 bar:...

...bool %matches(ubyte* %begin, ubyte* %end) { entry: %scan_end = getelementptr ubyte* %end, int -1 ; <ubyte*> [#uses=1] br label %loop_test regex6: ; preds = %loop_test %c8 = load ubyte* %iter ; <ubyte> [#uses=1] %matches9 = seteq ubyte %c8, 97 ; <bool> [#uses=1] br bool %matches9, label %ret_true, label %regex2 regex2: ; preds = %regex6 %c = load ubyte* %iter ; <ubyte> [#uses=1] %matches = seteq ubyte %c, 98 ; <bool> [#uses=1] br bool...

...[ %indvar.next, %bb3 ] ; <uint> [#uses=2] %sum.0.pn = phi int [ %sum.1, %bb3 ], [ %sum.0.pn.ph, %bb8.outer ] ; <int> [#uses=1] %i.0.pn = phi int [ 2, %bb3 ], [ %i.0.0.ph, %bb8.outer ] ; <int> [#uses=1] %sum.1 = add int %i.0.pn, %sum.0.pn ; <int> [#uses=3] %exitcond = seteq uint %indvar, 3 ; <bool> [#uses=1] br bool %exitcond, label %bb10, label %bb3 bb10: ; preds = %bb8 %indvar.next27 = add uint %indvar26, 1 ; <uint> [#uses=2] %exitcond28 = seteq uint %indvar.next27, 10 ; <bool> [#uses=1] br bool %exitcond28, label %bb16, label %bb8.outer...

It looks like createCFGSimplificationPass was disabled on 2006/09/04. This causes some problems for architectures that use conditional moves to implement select (alpha and ARM). For example, on 2006/09/03 a "if (a) return 0; else return 1;" compiled to ---------------------------------------- zapnot $17,15,$1 zapnot $16,15,$2 bis $31,$31,$0 cmpeq $2,$1,$1

...r quick answer :-). Am Freitag, 12. Mai 2006 19:09 schrieb Chris Lattner: > On Fri, 12 May 2006, Silken Tiger wrote: > > To find the first instructions which are not depending on others results. > > So far it seems to be working but i am missing instructions like: > > %tmp.1 = seteq int %argc, 2 ; <bool> [#uses=1] > > There seems only an function like llvm::Instruction::mayWriteToMemory > > but nothing like llvm::Instruction::mayReadFromMemory or s.t. with > > similiar functionality? > > > > Or else: if there is an even easier wa...

Hello LLVM Developers, I am working on an architecture which have one bit shift operation if barrel shiftier hardware is not present in such cases some DAGCombine optimizations reduces performance of certain benchmarks upto 5% for example consider follwing optimization: fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) Here it introduce 2 shift operations and when barrel shiftier is not present these shifts will be converted to loops thus making it worst. I am sure there few architectures which have similar features. So how to disable these kind of optimizations in...

...uble chosen to show a size that X86 can scale "for free"): #include <complex.h> void test(unsigned N, complex double *P) { for (; N != 0; --N) *P++ = 0; } We compile it to this LLVM code: void %test(uint %N, "complex long double"* %P) { entry: %tmp.15 = seteq uint %N, 0 ; <bool> [#uses=1] br bool %tmp.15, label %return, label %no_exit no_exit: ; preds = %no_exit, %entry %indvar = phi uint [ %indvar.next, %no_exit ], [ 0, %entry ] ; <uint> [#uses=3] %tmp.4 = getelementptr &quo...

...VM IR. Running > llvm->llvm passes breaks this property. I see that this is a desired property. If I recall correctly, you need this to remove the remaining annotations. Maybe llvm-gcc should run CFGSimplification. It would then compile "if (a) return 0; else return 1" into %tmp = seteq int %a, 0 %tmp1 = select bool %tmp, int 0, int 1 ret int %tmp1 Thanks, Rafael

I am attempting to match setcc using tablegen w/ the following patterns: def FEQ : Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0, GPRF32:$src1), "eq $dst, $src0, $src1", [(set GPRF32:$dst, (seteq GPRF32:$src0, GPRF32:$src1))]>; And it is failing stating that the result must be an integer. Is there a way around this other than modifying TargetSelectionDAG.td? Also, why is it assumed that all comparison results are always integers? If I put GPRI32 as my destination register, it compla...