search for: setccresulttyp

I converted now my back-end with legal i1 lowering to the 2.6 branch and my original problem with the DAG combiner didn't occur any more and seems to be fixed. setOperationAction(ISD::OR, MVT::i1, Promote) also works fine for logical operations. > What is your SetCCResultType now? I changed SetCCResultType to return MVT::i1 type. > Can you compile the CodeGen/Blackfin/basic-i1.ll test case? I never > got that one working with legal i1. The IA64 back-end couldn't compile > it either. No, I was not able to compile your basic-i1.ll test case but I thi...

On 24/08/2009, at 01.19, Stripf, Timo wrote: > > I had also a lot of problems to get the i1 operations working. E.g. > I had to override the getSetCCResultType to get is working and for > ADDE/ADDC the i1 target registers are hardcoded. What is your SetCCResultType now? Can you compile the CodeGen/Blackfin/basic-i1.ll test case? I never got that one working with legal i1. The IA64 back-end couldn't compile it either. > I'm writing...

...> It just happens to always hold the values 0 and 1. The i1 logical > operations are rarely needed, and they can be custom inserted when > necessary, see BlackfinTargetLowering::LowerADDE(). I had also a lot of problems to get the i1 operations working. E.g. I had to override the getSetCCResultType to get is working and for ADDE/ADDC the i1 target registers are hardcoded. I'm writing the back-end to research the influence of several ISA characteristics on the processor performance. Large parts of my back-end are automatically generated by a general description. So I'm very intereste...