search for: setcc

Displaying 20 results from an estimated 202 matches for "setcc".

2017 Jul 21
4
Issue with DAG legalization of brcond, setcc, xor
But isn't kinda silly that we transform to xor and then we transform it back. What is the advantage in doing so? Also, since we do that method, I now have to introduce setcc patterns for i1 values, instead of being able to just use logical pattern operators like not. -Dilan On Fri, Jul 21, 2017 at 11:00 AM Dilan Manatunga <manatunga at gmail.com> wrote: > For some reason I didn't get Krzysztof Parzyszek e-mail in my inbox, but > thanks for the fact I...
2017 Jul 20
3
Issue with DAG legalization of brcond, setcc, xor
...reg79 t15: i32,ch = CopyFromReg t0, Register:i32 %vreg1 t16: ch = llvm.tpu.dma.write.1KB.async t0, TargetConstant:i32<4602>, t10, t12, t15 t18: i32,ch = CopyFromReg t0, Register:i32 %vreg166 t20: i32 = AssertZext t18, ValueType:ch:i1 t23: i1 = setcc t20, Constant:i32<0>, seteq:ch t25: i32,ch = CopyFromReg t0, Register:i32 %vreg396 t28: i1 = setcc t25, Constant:i32<255>, setugt:ch t29: i1 = and t23, t28 t37: i1 = setcc t29, Constant:i1<-1>, setne:ch t33: ch = brcond t16, t37, BasicBlock:...
2009 Mar 22
3
[LLVMdev] Flags/ConditionCode Model is broken
Hi all, I've spent the day trying to understand setcc/select_cc intricacies, and I thought I should mention that so far as I can tell, the modeling of CPU flags, condition codes and therefore conditional instructions seems pretty broken. On the one hand there are the SDNPInFlag/SDNPOutFlag node properties which allow you to mark an instruction as usi...
2011 Apr 15
1
[LLVMdev] Confusion over ISelLowering of setcc
...0x3451540: ch = BasicBlock<else 0x344c230> 0x3451140: ch = brcond 0x34341a8, 0x3451a40, 0x3451540 This then gets lowered to this: 0x3741240: i1,ch = CopyFromReg 0x37241a8, 0x3741640 0x3741340: i1 = Constant<-1> 0x3741940: ch = setne 0x3741740: i1 = setcc 0x3741240, 0x3741340, 0x3741940 0x3741540: ch = BasicBlock<else 0x373c230> 0x3741140: ch = brcond 0x37241a8, 0x3741740, 0x3741540 And finally gets optimised to this: 0x3741240: i1,ch = CopyFromReg 0x37241a8, 0x3741640 [ID=6] 0x3741340: i1 = Constant<-1> [ID=2...
2014 Jul 06
2
[LLVMdev] LLVM commit 410f38e01597120b41e406ec1cea69127463f9e5
OK, so in you case, you want DAG.getSExtOrTrunc(SetCC, DL, SelectVT) to tunc the result from i64 to i32 on 64 bits targets, if I understand correctly. 2 questions: - Why not generating a selectcc node directly ? It avoid having to mess up with intermediate values. - Why calling getSetCCResultType(VT) ? VT is not the type of a parameter of setcc, an...
2014 Jul 08
2
[LLVMdev] LLVM commit 410f38e01597120b41e406ec1cea69127463f9e5
OK from what I understand, the DAG.getSExtOrTrunc(SetCC, DL, SelectVT) is unecessary and the SelectVT is nto the right type (as it is called with incorrect parameter). Here is a patch so it won't generate a loop. I ran make check and it doesn't look like anything is broken. 2014-07-07 11:36 GMT-07:00 Matt Arsenault <arsenm2 at gmail.com&gt...
2008 Dec 12
4
[LLVMdev] i1 promotion issue (again)
Background: The Cell SPU does not have condition registers in the normal sense. It fits the "zero or negative one" model, preferably with an i32 register, which is what getSetCCResultType() will return. Problem: LegalizeTypes promotes i1 to i8 via an i32 setcc, i.e., the generated type legalization is: (i8:truncate (i32:setcc i32:lhs, i32:rhs, ch:cond)) How do I keep DAGTypeLegalizer::PromoteIntRes_SETCC() from inserting the truncate without blowing all other type...
2014 Jul 05
2
[LLVMdev] LLVM commit 410f38e01597120b41e406ec1cea69127463f9e5
Hi, I'm working on a target which have a variable size for CC (the same size as the arguments). As a result getSetCCResultType, return a variable size. In this commit, at the line DAG.getSExtOrTrunc(SetCC, DL, SelectVT), on my target, you end up generating the Node you are replacing, and so creating a loop in the DAG, which give a whole new meaning to the A in the acronym. Subsequent code manipulating the DAG to...
2008 Jun 06
3
[LLVMdev] Variable length condition code for SETCC and SELECT?
...ntend to build. I've now discovered a new and interesting problem that I'm not sure how to solve cleanly and it's due to the fact that CellSPU has no fixed size condition flags. CellSPU's condition flags depend on the size of what's being compared, i.e., if both arguments to SETCC are i32, then a corresponding i32 comparison should be generated. Similarly, if both arguments to SETCC are i16 or i8, then a corresponding i16 or i8 comparison should be generated. Another nice feature in the CellSPU architecture is the selb instruction that directly corresponds to SELECT. Ag...
2013 Mar 05
4
[LLVMdev] Vector splitting vs widening
...rize node result 0: 0x2348420: v1f32 = extract_subvector 0x23434a0, 0x2348320 [ID=0] Scalarize node result 0: 0x2348220: v1f32 = extract_subvector 0x23434a0, 0x23466e0 [ID=0] Split node result: 0x23469e0: v4f32 = extract_subvector 0x23435a0, 0x23466e0 [ID=0] Split node operand: 0x2346be0: v4i1 = setcc 0x23467e0, 0x23469e0, 0x23436a0 [ID=0] Split node result: 0x2348620: v2f32 = extract_subvector 0x23435a0, 0x2346de0 [ID=0] Widen node result 0: 0x2348820: v2i1 = setcc 0x2346ee0, 0x2348620, 0x23436a0 [ID=0] llc: lib/CodeGen/SelectionDAG/LegalizeTypes.h:599: llvm::SDValue llvm::DAGTypeLegalizer::...
2009 Dec 11
2
[LLVMdev] combine ISD::SETCC by custom routine
hi, i have a backend that want to do custom combine on SETCC nodes. but some time SETCC was combined into BR_CC before i can visit it to do my own combine, because DAGCombiner always do its own combine before custom combine. so, is there anyway to prevent it being combined without changing the logic of DAGCombiner? thank you very much --ether
2014 Jul 08
2
[LLVMdev] LLVM commit 410f38e01597120b41e406ec1cea69127463f9e5
2014-07-08 12:11 GMT-07:00 Matt Arsenault <Matthew.Arsenault at amd.com>: > On 07/07/2014 09:47 PM, deadal nix wrote: > > OK from what I understand, the DAG.getSExtOrTrunc(SetCC, DL, SelectVT) > is unecessary and the SelectVT is nto the right type (as it is called with > incorrect parameter). > > Here is a patch so it won't generate a loop. I ran make check and it > doesn't look like anything is broken. > > No, it is necessary and is the funda...
2014 Jul 08
2
[LLVMdev] LLVM commit 410f38e01597120b41e406ec1cea69127463f9e5
On 07/08/2014 03:20 PM, Matt Arsenault wrote: > Alternatively maybe this should only be done if the setcc type is the > same as the sext result? I think we should actually do this. If you need to convert the setcc result after, you aren't really gaining anything by doing this transformation -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.o...
2013 Mar 09
1
[LLVMdev] Vector splitting vs widening
...lt;llvmdev at cs.uiuc.edu> > Sent: Wednesday, March 6, 2013 3:40:50 PM > Subject: Re: [LLVMdev] Vector splitting vs widening > > Hi Hal, > > > > > > > The problem is essentially the following: there are no vector f32 > types (yet), so the <v4i1> = setcc <v4f32> node needs to be split > and scalarized. The operand splitting seems to start correctly, but > because <v4i1> is itself a legal type, after splitting the node into > <v2i1> = setcc <v2f32>, the process becomes confused. The operands > are again split (as...
2008 Oct 25
0
[LLVMdev] SetCC tablegen pattern
That's how ISD::SETCC is specified. If you want to change that for your target, you should custom lower these nodes to target nodes. Then you can specify your own SDNode with your own SDTypeProfile. Evan On Oct 24, 2008, at 4:31 PM, Villmow, Micah wrote: > I am attempting to match setcc using tablegen w/ the...
2008 Oct 24
2
[LLVMdev] SetCC tablegen pattern
I am attempting to match setcc using tablegen w/ the following patterns: def FEQ : Instruction<(outs GPRF32:$dst), (ins GPRF32:$src0, GPRF32:$src1), "eq $dst, $src0, $src1", [(set GPRF32:$dst, (seteq GPRF32:$src0, GPRF32:$src1))]>; And it is failing stating that the result must be an integer. Is the...
2009 Dec 11
0
[LLVMdev] combine ISD::SETCC by custom routine
On Fri, Dec 11, 2009 at 1:49 AM, ether zhhb <etherzhhb at gmail.com> wrote: > hi, > > i have a backend that want to do custom combine on SETCC nodes. > > but some time SETCC was combined into BR_CC before i can visit it to > do my own combine, because DAGCombiner always do its own combine > before custom combine. so, is there anyway to prevent it being > combined without changing the logic of DAGCombiner? If BR_CC isn'...
2013 Jul 01
1
[LLVMdev] Convert the result of a vector comparison into a scalar bit mask?
When LLVM does a comparison of two vectors, in this case with 16 elements, the returned type of setcc is v16i1. The architecture I'm targeting allows storing the result of a vector comparison as a bit mask in a scalar register, but I'm having trouble converting the result of setcc into a value that is usable there. For example, if I try to AND together masks that are the results of two com...
2010 Oct 02
1
[LLVMdev] Illegal optimization in LLVM 2.8 during SelectionDAG? (Re: comparison pattern trouble - might be a bug in LLVM 2.8?)
...removeFromWorkList(TheXor); >> DAG.DeleteNode(TheXor); >> return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), >> MVT::Other, Chain, Tmp, N2); >> } >> } >> >> if (Op0.getOpcode() != ISD::SETCC&& Op1.getOpcode() != ISD::SETCC) { >> bool Equal = false; >> if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) >> if (RHSCI->getAPIntValue() == 1&& Op0.hasOneUse()&& >> Op0.getOpcode() == ISD::XO...
2013 Mar 06
0
[LLVMdev] Vector splitting vs widening
Hi Hal, > The problem is essentially the following: there are no vector f32 types (yet), so the <v4i1> = setcc <v4f32> node needs to be split and scalarized. The operand splitting seems to start correctly, but because <v4i1> is itself a legal type, after splitting the node into <v2i1> = setcc <v2f32>, the process becomes confused. The operands are again split (as they should be), but...