Displaying 4 results from an estimated 4 matches for "setbooleanvectorcont".
2020 Feb 19
2
i1 true ^= -1 in DAG matcher?
...TOR will
just point to the same ConstantSDNode for each element. There is no concept
of a sign in the storage. It's just a bit. Whether or not its treated as 1
or negative 1 is going to depend on the code looking at the value including
printing code. And nothing in the printing code knows
about setBooleanVectorContents so it can't make any decisions about how to
print it either. I believe SelectionDAGDumper just calls
APInt::operator<<(raw_ostream &) which defaults to printing signed.
~Craig
On Wed, Feb 19, 2020 at 3:01 PM Hendrik Greving <
hendrik.greving.smi at gmail.com> wrote:
>...
2020 Feb 19
2
i1 true ^= -1 in DAG matcher?
...mp ne <8 x i32> %6, %5
> > %7 = xor <8 x i1> %cmp4.i, <i1 true, i1 true, i1 true, i1 true, i1 true,
> i1 true, i1 true, i1 true>
> > [use of %7]
> >
> > results in vector of '-1' in the DAG.
>
> This should be controlled by TargetLowering::setBooleanVectorContents,
> which lets each target choose whether a boolean is 0/1 or 0/-1 when
> held in a larger register. For AMDGPU it looks like R600 wants 0/-1,
> but SIL wants 0/1 so if you're seeing -1 when compiling for a SIL
> target that's probably a bug.
>
> Cheers.
>
> Tim....
2020 Feb 19
2
i1 true ^= -1 in DAG matcher?
Hello,
It looks like that in the DAG matcher, the DAG has a xor with '-1' for
checking a true value vector
for instance,
%cmp4.i = icmp ne <8 x i32> %6, %5
%7 = xor <8 x i1> %cmp4.i, <i1 true, i1 true, i1 true, i1 true, i1 true, i1
true, i1 true, i1 true>
[use of %7]
results in vector of '-1' in the DAG. This also seems the reason why
LLVM's vnot PatFrag
2013 Sep 25
1
[LLVMdev] arm64 / iOS support
...&TM)
: TargetLowering(TM, createTLOF(TM)), Itins(TM.getInstrItineraryData()) {
-
- const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>();
-
+ Subtarget = &TM.getSubtarget<AArch64Subtarget>();
// SIMD compares set the entire lane's bits to 1
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
@@ -2050,6 +2050,90 @@ AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
}
}
+SDValue
+AArch64TargetLowering::LowerGlobalAddressDarwin(SDValue Op,
+ SelectionDAG &DAG) const {
+
+ EVT PtrVT...