Displaying 6 results from an estimated 6 matches for "setbooleancont".
2010 Jan 20
0
[LLVMdev] [LLVMDev] Is there any way to eliminate zero-extension instruction?
...> We think that r3 is not necessary. Is there any way to eliminate it by just modifying
>
> our backend?
>
> Thank you in advance.
>
> Minwook Ahn
Have you told LLVM the result of setcc operations is 0 or 1? Add the following to the constructor of your ISelLowering class:
setBooleanContents(ZeroOrOneBooleanContent);
--
Richard Osborne | XMOS
http://www.xmos.com
2010 Jan 20
2
[LLVMdev] [LLVMDev] Is there any way to eliminate zero-extension instruction?
Dear developers.
We try to make our own backend of llvm for our target machine.
Assume that we have the following code in our source code.
int i = ( a < b );
The code is translated into
r0 <- gt r1 r2
r3 <- and r0 0x1
We think that r3 is not necessary. Is there any way to eliminate it by just
modifying
our backend?
Thank you in advance.
Minwook Ahn
-------------- next part
2012 May 22
2
[LLVMdev] Predicate registers/condition codes question
...s going
> wrong; are you sure there isn't anything in your target still
> expecting an i1?
I have specified that Hexagon has an i8 predicate register that
represents the true predicate as -1 with a sign extend like this:
addRegisterClass(MVT::i8, &Hexagon::PredRegsRegClass);
setBooleanContents(ZeroOrNegativeOneBooleanContent);
and I'm calling this code just before computeRegisterProperties, that
builds the TransformToType table specifying the type promotions:
i1 -> i8
i8 -> i8 (legal)
i16 -> i32
i32 -> i32 (legal)
This would be fine if the register for i8 could b...
2012 May 22
0
[LLVMdev] Predicate registers/condition codes question
...there isn't anything in your target still
>> expecting an i1?
>
> I have specified that Hexagon has an i8 predicate register that
> represents the true predicate as -1 with a sign extend like this:
>
> addRegisterClass(MVT::i8,&Hexagon::PredRegsRegClass);
> setBooleanContents(ZeroOrNegativeOneBooleanContent);
>
> and I'm calling this code just before computeRegisterProperties, that
> builds the TransformToType table specifying the type promotions:
>
> i1 -> i8
> i8 -> i8 (legal)
> i16 -> i32
> i32 -> i32 (legal)
>
>...
2012 Mar 01
0
[LLVMdev] Predicate registers/condition codes question
On Tue, Feb 28, 2012 at 11:17 AM, Tony Linthicum <tlinth at codeaurora.org> wrote:
> Hey folks,
>
> We are having some difficulty with how we have been representing our
> predicate registers, and wanted some advice from the list. First, we
> had been representing our predicate registers as 1 bit (i1). The truth,
> however, is that they are 8 bits. The reason for this is
2012 Feb 28
3
[LLVMdev] Predicate registers/condition codes question
Hey folks,
We are having some difficulty with how we have been representing our
predicate registers, and wanted some advice from the list. First, we
had been representing our predicate registers as 1 bit (i1). The truth,
however, is that they are 8 bits. The reason for this is that they
serve as predicates for conditional execution of instructions, branch
condition codes, and also as