search for: set_pte

If we're building a pte, we can use simple assigment; only use set_pte etc. when we're actually going to use that destination as a PTE. I don't know that we'll ever run under Xen, but it's neater. And use set_pte/set_pmd rather than assuming native_ versions, even though that's probably true for most people. (Includes compile fix by Kamalesh Bab...

If we're building a pte, we can use simple assigment; only use set_pte etc. when we're actually going to use that destination as a PTE. I don't know that we'll ever run under Xen, but it's neater. And use set_pte/set_pmd rather than assuming native_ versions, even though that's probably true for most people. (Includes compile fix by Kamalesh Bab...

...nooping a partially written PTE and getting a bad mapping installed. Signed-off-by: Zachary Amsden <zach@vmware.com> =================================================================== --- a/include/asm-i386/pgtable-2level.h +++ b/include/asm-i386/pgtable-2level.h @@ -16,6 +16,7 @@ #define set_pte(pteptr, pteval) (*(pteptr) = pteval) #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) #define set_pte_atomic(pteptr, pteval) set_pte(pteptr,pteval) +#define set_pte_present(mm,addr,ptep,pteval) set_pte_at(mm,addr,ptep,pteval) #define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))...

On x86 set_pte_at() is now always falling back to set_pte(). So instead of having this fallback after the paravirt maze just drop the set_pte_at paravirt operation and let set_pte_at() use the set_pte() function directly. Signed-off-by: Juergen Gross <jgross at suse.com> --- arch/x86/include/asm/paravirt....

...ts to V1 - new patches 3 and 4 Juergen Gross (6): x86/paravirt: remove 32-bit support from PARAVIRT_XXL x86/paravirt: cleanup paravirt macros x86/paravirt: use CONFIG_PARAVIRT_XXL instead of CONFIG_PARAVIRT x86/entry/32: revert "Fix XEN_PV build dependency" x86/paravirt: remove set_pte_at pv-op x86/paravirt: avoid needless paravirt step clearing page table entries arch/x86/entry/entry_64.S | 4 +- arch/x86/entry/vdso/vdso32/vclock_gettime.c | 1 + arch/x86/include/asm/fixmap.h | 2 +- arch/x86/include/asm/idtentry.h | 4 +-...

Now that ptep_establish has a definition in PAE i386 3-level paging code, the only paging model which is insane enough to have multi-word hardware PTEs which are not efficient to set atomically, we can remove the ghost of set_pte_atomic from other architectures which falesly duplicated it, and remove all knowledge of it from the generic pgtable code. set_pte_atomic is now a private pte operator which is specific to i386 Signed-off-by: Zachary Amsden <zach@vmware.com> ================================================...

...00 @@ -8,17 +8,6 @@ #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) -/* - * Certain architectures need to do special things when PTEs - * within a page table are directly modified. Thus, the following - * hook is made available. - */ -#define set_pte(pteptr, pteval) (*(pteptr) = pteval) -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) -#define set_pte_atomic(pteptr, pteval) set_pte(pteptr,pteval) -#define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval)) - -#define ptep_get_and_clear(mm,addr,xp) __pte(xchg(&(xp)->pte_low, 0))...

...00 @@ -8,17 +8,6 @@ #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) -/* - * Certain architectures need to do special things when PTEs - * within a page table are directly modified. Thus, the following - * hook is made available. - */ -#define set_pte(pteptr, pteval) (*(pteptr) = pteval) -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) -#define set_pte_atomic(pteptr, pteval) set_pte(pteptr,pteval) -#define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval)) - -#define ptep_get_and_clear(mm,addr,xp) __pte(xchg(&(xp)->pte_low, 0))...

Robert P. J. Day wrote: > Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> > > --- > > diff --git a/arch/i386/kernel/vmi.c b/arch/i386/kernel/vmi.c Maintainers are apparently those under "PARAVIRT_OPS INTERFACE". CCs added. > index c12720d..e3ce5c8 100644 > --- a/arch/i386/kernel/vmi.c > +++ b/arch/i386/kernel/vmi.c > @@ -235,7 +235,7 @@ static

Robert P. J. Day wrote: > Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> > > --- > > diff --git a/arch/i386/kernel/vmi.c b/arch/i386/kernel/vmi.c Maintainers are apparently those under "PARAVIRT_OPS INTERFACE". CCs added. > index c12720d..e3ce5c8 100644 > --- a/arch/i386/kernel/vmi.c > +++ b/arch/i386/kernel/vmi.c > @@ -235,7 +235,7 @@ static

Hey folks, This is the part-of-pvops-implementation-that-is-not-exactly-a-merge. Neat, uh? This is the majority of the work. The first patch in the series does not really belong here. It was already sent to lkml separetedly before, but I'm including it again, for a very simple reason: Try to test the paravirt patches without it, and you'll fail miserably ;-) (and it was not yet

Hey folks, This is the part-of-pvops-implementation-that-is-not-exactly-a-merge. Neat, uh? This is the majority of the work. The first patch in the series does not really belong here. It was already sent to lkml separetedly before, but I'm including it again, for a very simple reason: Try to test the paravirt patches without it, and you'll fail miserably ;-) (and it was not yet

...s paravirt_ops = { .flush_tlb_kernel = native_flush_tlb_global, .flush_tlb_single = native_flush_tlb_single, + .alloc_pt = (void *)native_nop, + .alloc_pd = (void *)native_nop, + .alloc_pd_clone = (void *)native_nop, + .release_pt = (void *)native_nop, + .release_pd = (void *)native_nop, + .set_pte = native_set_pte, .set_pte_at = native_set_pte_at, .set_pmd = native_set_pmd, =================================================================== --- a/arch/i386/mm/init.c +++ b/arch/i386/mm/init.c @@ -62,6 +62,7 @@ static pmd_t * __init one_md_table_init( #ifdef CONFIG_X86_PAE pmd_table...

...s paravirt_ops = { .flush_tlb_kernel = native_flush_tlb_global, .flush_tlb_single = native_flush_tlb_single, + .alloc_pt = (void *)native_nop, + .alloc_pd = (void *)native_nop, + .alloc_pd_clone = (void *)native_nop, + .release_pt = (void *)native_nop, + .release_pd = (void *)native_nop, + .set_pte = native_set_pte, .set_pte_at = native_set_pte_at, .set_pmd = native_set_pmd, =================================================================== --- a/arch/i386/mm/init.c +++ b/arch/i386/mm/init.c @@ -62,6 +62,7 @@ static pmd_t * __init one_md_table_init( #ifdef CONFIG_X86_PAE pmd_table...

...s paravirt_ops = { .flush_tlb_kernel = native_flush_tlb_global, .flush_tlb_single = native_flush_tlb_single, + .alloc_pt = (void *)native_nop, + .alloc_pd = (void *)native_nop, + .alloc_pd_clone = (void *)native_nop, + .release_pt = (void *)native_nop, + .release_pd = (void *)native_nop, + .set_pte = native_set_pte, .set_pte_at = native_set_pte_at, .set_pmd = native_set_pmd, =================================================================== --- a/arch/i386/mm/init.c +++ b/arch/i386/mm/init.c @@ -62,6 +62,7 @@ static pmd_t * __init one_md_table_init( #ifdef CONFIG_X86_PAE pmd_table...

...s paravirt_ops = { .flush_tlb_kernel = native_flush_tlb_global, .flush_tlb_single = native_flush_tlb_single, + .alloc_pt = (void *)native_nop, + .alloc_pd = (void *)native_nop, + .alloc_pd_clone = (void *)native_nop, + .release_pt = (void *)native_nop, + .release_pd = (void *)native_nop, + .set_pte = native_set_pte, .set_pte_at = native_set_pte_at, .set_pmd = native_set_pmd, =================================================================== --- a/arch/i386/mm/init.c +++ b/arch/i386/mm/init.c @@ -62,6 +62,7 @@ static pmd_t * __init one_md_table_init( #ifdef CONFIG_X86_PAE pmd_table...

...ble support (equivalent of arch/i386/mm/pgtable-xen.c) and mostly following Linux for the moment. I noticed that linux-2.6.18-xen never pins an L1 table (a pte), yet __pgd_pin() walks the page directory and gives up write access on the kernel mappings of pte pages and only pins the pgd page. How do set_pte() and set_pte_at() macros work if they are writing directly to the page table entires ? do we fault in the kernel to handle this ?! thanks, satya. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Chris Wright wrote: >* Zachary Amsden (zach@vmware.com) wrote: > > >>Does Xen assume page aligned descriptor tables? I assume from this >> >> > >Yes. > > > >>patch and snippets I have gathered from others, that is a yes, and other >>things here imply that DT pages are not shadowed. If so, Xen itself >>must have live segments

Chris Wright wrote: >* Zachary Amsden (zach@vmware.com) wrote: > > >>Does Xen assume page aligned descriptor tables? I assume from this >> >> > >Yes. > > > >>patch and snippets I have gathered from others, that is a yes, and other >>things here imply that DT pages are not shadowed. If so, Xen itself >>must have live segments

..., - .flush_tlb_kernel = native_flush_tlb_global, - .flush_tlb_single = native_flush_tlb_single, - .flush_tlb_others = native_flush_tlb_others, - - .alloc_pt = paravirt_nop, - .alloc_pd = paravirt_nop, - .alloc_pd_clone = paravirt_nop, - .release_pt = paravirt_nop, - .release_pd = paravirt_nop, - - .set_pte = native_set_pte, - .set_pte_at = native_set_pte_at, - .set_pmd = native_set_pmd, - .pte_update = paravirt_nop, - .pte_update_defer = paravirt_nop, + }, + + .pv_misc_ops = { + .set_lazy_mode = paravirt_nop, + }, + + .pv_mmu_ops = { + .read_cr2 = native_read_cr2, + .write_cr2 = native_write_...