Displaying 3 results from an estimated 3 matches for "set_dst".
2009 Sep 10
0
[PATCH 06/13] nv50: handle SEQ, SGT, SLE, SNE opcodes
...t;< breaks things.. .u32 by default?
+ e->inst[1] |= 0x60000000 | (ccode << 14);
+
+ /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but
+ * that doesn't seem to match what the hw actually does
+ e->inst[1] |= 0x04000000; << breaks things, u32 by default ?
*/
- set_dst(pc, dst, e);
+
+ if (wp >= 0)
+ set_pred_wr(pc, 1, wp, e);
+ if (dst)
+ set_dst(pc, dst, e);
+ else {
+ e->inst[0] |= 0x000001fc;
+ e->inst[1] |= 0x00000008;
+ }
+
set_src_0(pc, src0, e);
set_src_1(pc, src1, e);
- emit(pc, e);
- /* cvt.f32.u32 */
- e = exec(pc);
- e->inst[0] =...
2009 Jun 21
0
[PATCH] nv50: support for SLE, SNE, SEQ, SGT
...3 << 29);
- e->inst[1] |= (c_op << 14);
- /*XXX: breaks things, .u32 by default?
- * decuda will disasm as .u16 and use .lo/.hi regs, but this
- * doesn't seem to match what the hw actually does.
- inst[1] |= 0x04000000; << breaks things.. .u32 by default?
- */
- set_dst(pc, dst, e);
+ e->inst[1] |= 0x60000000;
+ /* XXX: decuda will disasm .u16 lo/hi,
+ * but 32 bit flag breaks things: */
+ /* e->inst[1] |= 0x04000000; */
+ e->inst[1] |= (map_ccode_nv50(c_op) << 14);
+
+ if (wp >= 0)
+ set_pred_wr(pc, 1, wp, e);
+ if (dst)
+ set_dst(pc, ds...
2009 May 06
2
nv50: shader generation patches
Hi ! I've been trying to improve NV50 shader generation a bit the last couple of weeks, so here is
what I've produced. I don't know if it's usable for you or just a pile of horrible hacks, but at
least it makes some mesa demos render more correcly, p.e. the teapot (aside from mip-mapping issues
of the floor texture), arbfplight, and I think the gears also didn't appear as they