Displaying 12 results from an estimated 12 matches for "seshadri".
2005 Jan 05
4
TC GUI or graphs?
...raph the data sent through all configured classes or
qdiscs.
I could not find anything. Could someone tell me if a GUI exists or a
graphing utility for tc? If my post is a repeat, could someone tell me where
the archive is? I''ll search the archive, before posting here.
Thank you,
Deepak Seshadri
_______________________________________________
LARTC mailing list / LARTC@mailman.ds9a.nl
http://mailman.ds9a.nl/mailman/listinfo/lartc HOWTO: http://lartc.org/
2017 Sep 05
4
Lowering llvm.memset for ARM target
As reported in an earlier thread
(http://clang-developers.42468.n3.nabble.com/Disable-memset-synthesis-tp4057810.html),
we noticed in some cases that the llvm.memset intrinsic, if lowered to
stores, could help with performance.
Here's a test case: If LIMIT is > 8, I see that a call to memset is
emitted for arm & aarch64, but not for x86 target.
typedef struct {
int v0[100];
}
2017 Aug 16
2
[cfe-dev] Disable memset synthesis
On Tue, Aug 15, 2017 at 9:37 PM, Tim Northover via cfe-dev <
cfe-dev at lists.llvm.org> wrote:
> On 15 August 2017 at 19:38, bharathi seshadri via llvm-dev
> <llvm-dev at lists.llvm.org> wrote:
> > I find that GCC has an option -fno-tree-loop-distribute-patterns that
> > can be used to disable memcpy/memset synthesis. I wonder if there is
> > something similar in llvm/clang.
>
> I have no idea what that me...
2005 Feb 10
2
How to save ip route 2 commands
...to know if there is a way to save these commands
through the IP route 2 utility. Doesn''t ip route 2 utility offer a way to
save the configurations/commands? Does it save the settings in some files,
may be in /etc or some directory?
Any help will be greatly appreciated.
Thank you,
Deepak Seshadri
Technical Support Engineer
Broadband Maritime, Inc.
61 Broadway, Suite 1905
New York, NY 10006
Tel: 1-212-405-1055
Fax: 1-212-214-0949
E-mail: dseshadri@broadbandmaritime.com
This message is for the named person''s use only. It may contain
confidential, proprietary or legally privileged ma...
2017 Aug 17
3
[cfe-dev] Disable memset synthesis
...--paulr
>
>
>
> *From:* cfe-dev [mailto:cfe-dev-bounces at lists.llvm.org] *On Behalf Of *Reid
> Kleckner via cfe-dev
> *Sent:* Wednesday, August 16, 2017 1:39 PM
> *To:* Tim Northover
> *Cc:* LLVM Developers Mailing List; cfe-dev at lists.llvm.org Developers;
> bharathi seshadri
> *Subject:* Re: [cfe-dev] [llvm-dev] Disable memset synthesis
>
>
>
> On Tue, Aug 15, 2017 at 9:37 PM, Tim Northover via cfe-dev <
> cfe-dev at lists.llvm.org> wrote:
>
> On 15 August 2017 at 19:38, bharathi seshadri via llvm-dev
> <llvm-dev at lists.llvm.org>...
2017 Aug 16
3
Disable memset synthesis
Our application is 32-bit big-endian ARM and we use -O3 with LTO.
clang optimizes certain initialization of structures to zero with
calls to memset, which are not further lowered to move instructions.
Investigating perf reports, it looks like it may be beneficial to
disable this optimization that introduces a function call to memset in
certain hot paths.
I tried passing -fno-builtin, but that
2018 Jun 29
2
Cleaning up ‘br i1 false’ cases in CodeGenPrepare
...totally makes sense to lower is.constant and
objectsize in the same place. I'm just saying that if the ideal piece of
code to do that isn't CGP, ...)
On Fri, Jun 29, 2018 at 12:21 PM Friedman, Eli via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 6/28/2018 9:44 PM, Bharathi Seshadri via llvm-dev wrote:
> > Hi,
> >
> > I have come across a couple of cases where the code generated after
> > CodeGenPrepare pass has "br i1 false .." with both true and false
> > conditions preserved and this propagates further and remains the same
> > i...
2018 Dec 04
2
Incorrect placement of an instruction after PostRAScheduler pass
Hi,
I’m facing a crash issue (--target=arm-linux-gnueabi
-march=armv8-a+crc -mfloat-abi=hard) and debugging the problem, I
found that an intended branch was not taken due to bad code generation
after the Post RA Scheduler pass. A CMPri instruction after an
INLINEASM block (which inturn contains a cmp, bne instruction) is
being moved before the INLINEASM block incorrectly resulting in two
2018 Jun 29
2
Cleaning up ‘br i1 false’ cases in CodeGenPrepare
Hi,
I have come across a couple of cases where the code generated after
CodeGenPrepare pass has "br i1 false .." with both true and false
conditions preserved and this propagates further and remains the same
in the final assembly code/executable.
In CodeGenPrepare::runOnFunction, ConstantFoldTerminator (which
handles the br i1 false condition) is called only once and if after
the
2006 Jul 25
3
problem in Route add using netlink
Hi all
Iam trying to implement "route add " using netlink. The changes are not reflected in the routing table. I have given my code and screen shots of the routing tables.
Can anybody tell me is there any mistake iam making in defining the fields .
or any other mistake iam commiting
thanxs
viji
//////////////////////////////////// CODE
2005 Jan 08
2
script
dear all
iam newbie , i have 256 kbits of down link and 64 kbits of up link iam using squid and htb i have got this while browsing the net , there are some few issues i need help
while running the script i want browsing to be as fast as possible , uplink especially kaaza should not eat my band width.
eth1 got public ip address and eth0 is internal with network 10.0.0.0/24 iam also using nat
2018 May 24
0
X86 Intrinsics : _mm_storel_epi64/ _mm_loadl_epi64 with -m32
Hi,
I’m using _mm_storel_epi64/ _mm_loadl_epi64 in my test case as below
and generating 32-bit code (using -m32 and -msse4.2). The 64-bit load
and 64-bit store operations are replaced with two 32-bit mov
instructions, presumably due to the use of uint64_t type. If I use
__m128i instead of uint64_t everywhere, then the read and write happen
as 64-bit operations using the xmm registers as expected.