Displaying 3 results from an estimated 3 matches for "series_vector".
2016 Nov 04
2
[RFC] Supporting ARM's SVE in LLVM
...Count EC, Value *Start,
Value* Step, const Twine &Name = "",
bool HasNUW = false, bool HasNSW = false);
```
### Fixed-Width Behaviour:
A constant vector is created with the same arithmetic series.
### SelectionDAG:
See [*ISD::SERIES_VECTOR*](#isdseriesvector).
## *test*
### Syntax:
`<result> = test <cond> <ty> <v1>`
### Overview:
This instruction returns a scalar boolean value based on the comparison of a
boolean or vector boolean operand. It allows us to reason about a value as a
whole rather than the pe...
2018 Jun 05
3
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...t; is the name Cray has traditionally used for this operation
> as it is the mathematical name for the concept. It's also used by C++
> and go and so should be familiar to many people.
Iota would be fine with me; I forget the reason we didn't go with that initially. We
also had 'series_vector' in the past, but that was a more generic form with start
and step parameters instead of requiring additional IR instructions to multiply and
add for the result as we do for stepvector.
>
>> Future Work
>> -----------
>>
>> Intrinsics cannot currently be used for c...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi,
Now that Sander has committed enough MC support for SVE, here's an updated
RFC for variable length vector support with a set of 14 patches (listed at the end)
to demonstrate code generation for SVE using the extensions proposed in the RFC.
I have some ideas about how to support RISC-V's upcoming extension alongside
SVE; I'll send an email with some additional comments on