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endian
2018 Dec 07
3
Implement VLIW Backend on LLVM (Assembler Related Questions)
...ction in this way:
add_type1 Ri, Rj, Rk
add_type2 Ri, Rj, Rk, Rl, Rm, Rn
add_type3 Ri, Rj, Rk, Rl, Rm, Rn, Ro, Rp, Rq
Q2.
Some of the instructions need to setup additional configuration, e.g.
{
scache wa ; Set cache mode: write allocate
ssize 64 ; Set write size = 64 bits
sendian big ; Set big endian writing
store R0, 0x1000000 ; Write "R0" to 0x1000000
}
So, again, parser has to parse the entire bundle to generate correct
encoding.
Or I should define my instruction in this way:
store R0, 0x1000000, wa, 64, big, .... (10 options can be set)
Q3.
The destinat...