Displaying 2 results from an estimated 2 matches for "selectmultiplication".
2017 Feb 27
2
When AVR backend generates mulsu instruction ?
...sults. This
> makes it quite hard to fit into TableGen and so we perform custom lowering
> for these nodes.
>
> We expand the MUL DAG node into 'ISD::UMUL_LOHI' or 'ISD::SMUL_LOHI'. We
> see these in AVRISelDAGToDAG.cpp and custom lower them (see
> AVRISelDAGToDAG::selectMultiplication) into MULSRdRr or MULRdRr,
> depending on signedness. Later on we have a custom inserter which inserts
> instructions to clear the r1,r0 scratch registers after use.
>
> The MULSURdRr instruction you mentioned is not generated by LLVM unless
> you use it yourself as part of some inli...
2017 Feb 26
2
When AVR backend generates mulsu instruction ?
Hello LLVMDevs,
I am looking for an example for how to lower LLVM IR to mulsu kind of
instruction. I found that AVR back end have such instruction but
AVRInstrInfo.td does not define any DAG pattern for which this
instruction gets emitted.
def MULSURdRr : FMUL2RdRr<1,
(outs),
(ins GPR8:$lhs, GPR8:$rhs),
"mulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
Also