Displaying 5 results from an estimated 5 matches for "selectiondagsel".
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selectiondagisel
2006 Oct 03
2
[LLVMdev] Questions about instruction selection and instruction definitions
...processors) does not support SELECT, so I was looking
for a workaround.
First I was thinking about expanding it into conditional flow with
branching, but then I have found that there exists a pass called
LowerSelect already.
I added in the getAnalysisUsage of my DAGtoDAGSel class (derived from
SelectionDAGSel) as a required analysis. After that, there are no more
SELECT instructions passed to my code selector, which is what I wanted.
Is it a correct to do it this way?
Anyhow, I have a very strong impression that after I did it, something
goes wrong with the code generations of copies from PHI nodes.
So...
2006 Oct 04
0
[LLVMdev] Questions about instruction selection and instruction definitions
..., so I was looking
> for a workaround.
>
> First I was thinking about expanding it into conditional flow with
> branching, but then I have found that there exists a pass called
> LowerSelect already.
>
> I added in the getAnalysisUsage of my DAGtoDAGSel class (derived from
> SelectionDAGSel) as a required analysis. After that, there are no more
> SELECT instructions passed to my code selector, which is what I wanted.
> Is it a correct to do it this way?
You can add the line
setOperationAction(ISD::SELECT, MVT::i32, Expand);
to the constructor of you TargetLowering class. See the...
2006 Oct 04
2
[LLVMdev] Questions about instruction selection and instruction definitions
....
> >
> > First I was thinking about expanding it into conditional flow with
> > branching, but then I have found that there exists a pass called
> > LowerSelect already.
> >
> > I added in the getAnalysisUsage of my DAGtoDAGSel class (derived
> from
> > SelectionDAGSel) as a required analysis. After that, there are no
> more
> > SELECT instructions passed to my code selector, which is what I
> wanted.
> > Is it a correct to do it this way?
> You can add the line
> setOperationAction(ISD::SELECT, MVT::i32, Expand);
> to the constructor o...
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
On Mon, 2 Oct 2006, Roman Levenstein wrote:
>>> Wouldn't it be possible and even more clean to have just one
>>> description like (I use a pseudo-description here):
>>>
>>> def MOVrr : I<0x88, MRMDestReg, (ops (GR8|GR16|GR32) :$dst,
>>> (i8mem|i16mem|i32mem):$src),
>>> "mov{b} {$src, $dst|$dst, $src}", []>,
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
Hi Chris,
Thanks a lot for your answer!
Chris Lattner wrote:
>> 1. Why does X86 instruction set description provide different
>> descriptions for the same instructions, which differ only in the
size
>> of operands?
>> E.g.
>>
>> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
>> "mov{b} {$src, $dst|$dst, $src}",