search for: selectiondag

...ment' : conversion from 'uint64_t' to 'unsigned int', possible loss of data ..\..\lib\CodeGen\MachineModuleInfo.cpp(1891) : warning C4244: 'initializing' : conversion from 'int64_t' to 'unsigned int', possible loss of dat DAGCombiner.cpp ..\..\lib\CodeGen\SelectionDAG\DAGCombiner.cpp(1802) : warning C4244: '=' : conversion from 'uint64_t' to 'unsigned int', possible loss of data ..\..\lib\CodeGen\SelectionDAG\DAGCombiner.cpp(2018) : warning C4244: 'argument' : conversion from 'uint64_t' to 'uint32_t', possible loss...

...0x00a483b8 in llvm::SmallVectorImpl<llvm::SDNode*>::pop_back_val (this=0x7ee90b38) at /export/home/karel/vcs/llvm-head/include/llvm/ADT/SmallVector.h:340 #3 0x00a6f074 in llvm::SDNode::isPredecessorOf (this=0x641bb08, N=0x6212a40) at /export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5703 #4 0x00a057c8 in CombineToPreIndexedLoadStore (this=0x7ee90f84, N=0x6238040) at /export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5707 #5 0x00a07544 in visitLOAD (this=0x7ee90f84, N=0x6238040) at /export/home/karel/vcs/llvm-head/lib/CodeG...

As I’m sure many of you have noticed, I no longer have the time to be a proper code owner for SelectionDAG. In the interest of the project and to keep development running smoothly, I am resigning my code ownership. Justin Bogner has graciously volunteered to take it up. He has a strong history of LLVM contributions, a demonstrated commitment to good community development practices, and has experience...

> > The other thing that might work, is having TargetMachine remember how > > the fast-isel option got set, and make OptLevelChanger do the right > > thing. But that seems like a hack to work around Mips not obeying the > > specified optimization level, honestly. > > I think we should do that as well. I don't think it's right that optnone > enables Fast

...ector operations; the idea is that this allows removing the code from LegalizeDAG that handles illegal types, which should be a significant simplification. There are still some issues with this patch, but does the approach look sane? -Eli -------------- next part -------------- Index: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (revision 0) +++ lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (revision 0) @@ -0,0 +1,243 @@ +//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::Legali...

...lVectorImpl<llvm::SDNode*>::pop_back_val > (this=0x7ee90b38) >     at /export/home/karel/vcs/llvm-head/include/llvm/ADT/SmallVector.h:340 > #3  0x00a6f074 in llvm::SDNode::isPredecessorOf (this=0x641bb08, > N=0x6212a40) >     at > /export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5703 > #4  0x00a057c8 in CombineToPreIndexedLoadStore (this=0x7ee90f84, > N=0x6238040) >     at > /export/home/karel/vcs/llvm-head/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5707 > #5  0x00a07544 in visitLOAD (this=0x7ee90f84, N=0x6238040) >     at > /export/home...

I'm still working on SSP support in LLVM. We have code that is in an IR pass StackProtector, SelectionDAG, FastISel, and some MachineFunction passes. Even in SelectiondDAG we have different code paths. I wonder if we can at least have only two code paths, one for SelectionDAG and the other for FastISel. IR pass may generate two forms of IR: 1) Almost pure IR, which contains only llvm.stackprotector th...

...fast-isel=false has no effect. I'm saying that optnone means 'use -O0 for this function' and that optnone should respect non-default values of the -fast-isel flag like -O0 does. This is the behaviour I'd expect: -fast-isel=false -fast-isel=default -fast-isel=true -O0 SelectionDAG FastISel FastISel -O0 + optnone attribute SelectionDAG* FastISel FastISel -O1 + optnone attribute SelectionDAG* FastISel FastISel -O2 + optnone attribute SelectionDAG* FastISel FastISel -O3 + optnone attribute SelectionDAG* FastISel FastISel -O1 SelectionDAG...

Hi, I've been experimenting with global isel over the last few weeks and it is such a vast improvement over the SelectionDAG for the AMDGPU target that I would really like to begin using it as soon as possible. Given the lack of a replacement for SelectionDAG's legalizer / combiner, and how much work this will be to implement, I think the fastest path to doing this would be to run some of the GlobalISel passes after...

...compile on Darwin now, I get this: $ /Volumes/Gir/devel/llvm/llvm-gcc-4.0.obj/gcc/xgcc <options> -o eh_alloc.o Assertion failed: (false && "Couldn't find the register class"), function getPhysicalRegisterRegClass, file /Volumes/Gir/devel/llvm/ llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp, line 269. ../../../../../llvm-gcc-4.0.src/libstdc++-v3/libsupc++/eh_alloc.cc: 182: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://llvm.org/bugs> for instructions. make[7]: *** [eh_alloc.lo] Error...

Here is a series of patches replacing EVT with MVT at a number of places in TargetLowering. The last two patches are related cleanups in SelectionDAGBuilder. /Patrik Hägglund > git log --stat --reverse origin/master.. commit 8dabe3eb005360347eabb86a2e88c3b6e9098ed5 Author: Patrik Hägglund <patrik.h.hagglund at ericsson.com> Date: Tue Dec 4 10:37:37 2012 +0100 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT...

...s from /home/dmikushin/sandbox/bin/llc...done. (gdb) r -march=nvptx64 test.ll Starting program: /home/dmikushin/sandbox/bin/llc -march=nvptx64 test.ll [Thread debugging using libthread_db enabled] This action is not supported yet! UNREACHABLE executed at /home/dmikushin/sandbox/src/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1198! Program received signal SIGABRT, Aborted. 0x00007ffff55ed3a5 in __GI_raise (sig=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:64 64 ../nptl/sysdeps/unix/sysv/linux/raise.c: No such file or directory. in ../nptl/sysdeps/unix/sysv/linux/raise.c (gdb) bt #0 0x00007ffff55ed3a5...

I am trying to understand the SelectionDAG construction from LLVM IR. I have gone through the doc "The LLVM Target-Independent Code Generator" on LLVM site. This gives a great initial overview. However I am unable to catch the actual control flow for the llvm->selectionDag conversion. The flags "-view-sched-dags".. d...

The diff is not only the && and || but also the leading !: diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 58f029fbe9fc..7ee06fc153b2 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -659,7 +659,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { (void)BlockNumber;...

new warnings, I think lib/CodeGen/SelectionDAG/DAGCombiner.cpp: In member function ‘llvm::SDValue<unnamed>::DAGCombiner::FindBetterChain(llvm::SDNode*, llvm::SDValue)’: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6006: warning: ‘SrcValueOffset’ may be used uninitialized in this function lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6006: no...

Hello all, I am currently working with LLVM and make use of the debug output from llc. The SelectionDAG dumping features are especially interesting to me since I am looking for operation patterns that allow me to decide which custom instructions can be added to a processor in order to improve the performance. Providing a -view-dag-combine1-dags option (and its friends) to llc show the SelectionD...

Hi Ankur, > The flags "-view-sched-dags".. described in the doc doesn't seem to work. ( > "llc -help" doesn't list it ). as far as I remember, displaying DAGs during compilation is only enabled in "debug builds" [1] of LLVM. You probably have to re-configure and re-compile LLVM to enable this feature. Best regards, Christoph [1]

On Apr 24, 2013, at 5:53 PM, Reed Kotler <rkotler at mips.com> wrote: > One question : > > "In the spirit of the (long-term) intent to migrate away from the > SelectionDAG framework" > > .. is this meant in general or just in respect to legalization? Everything. This includes all of the custom lowering code for all of the targets, all of dagcombine, and maybe all of the patterns in the TD files. -------------- next part -------------- An HTML attachment...

...port first-class functions, I've made the types of all functions a standard vararg (so I can box them). The implementation crashes when I try to read out the value of gc.result. Hints as to what might be wrong? Signed-off-by: Ramkumar Ramachandra <artagnon at gmail.com> --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 ++-- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 2 +- lib/CodeGen/SelectionDAG/StatepointLowering.cpp | 11 +++++++---- lib/IR/Verifier.cpp | 13 ++++++++----- test/CodeGen/X86/statepoint-call-lowering.ll | 17 ++++++++++++++++...

...some issues with this patch, but does > the approach look sane? New version with a few minor changes and fixed-up comments; the previous version had some comments with inaccurate statements, which might be confusing for reviewing. -Eli -------------- next part -------------- Index: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (revision 0) +++ lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (revision 0) @@ -0,0 +1,239 @@ +//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::Legali...