search for: selecti24

...able > to "see" that as a MUL i32 somewhere down the lowering process. > The R600 backend does something similar to this. It has 24-bit MUL and MAD instructions and selects these by looking at an i32 integer and trying to infer whether or not it is really a 24-bit value. See the SelectI24 and SelectU24 functions in AMDGPUISelDAGToDAG.cpp. -Tom > Are there suggestions on how to promote the type, but then be able to > customize the original i64 to a call and the original mul i32 to an > operation? > _______________________________________________ > LLVM Developers m...

I'll try to run through the scenario: 64-bit register type target (all registers have 64 bits). all 32-bits are getting promoted to 64-bit integers Problem: MUL on i32 is getting promoted to MUL on i64 MUL on i64 is getting expanded to a library call in compiler-rt the problem is that MUL32 gets promoted and then converted into a subroutine call because it is now type i64, even though

...; that as a MUL i32 somewhere down the lowering process. > > > > The R600 backend does something similar to this. It has 24-bit MUL and > MAD instructions and selects these by looking at an i32 integer and > trying to infer whether or not it is really a 24-bit value. > See the SelectI24 and SelectU24 functions in AMDGPUISelDAGToDAG.cpp. > > -Tom > > > > Are there suggestions on how to promote the type, but then be able to > > customize the original i64 to a call and the original mul i32 to an > > operation? > > > _____________________________...