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Hi, I'm not sure. But in your lowered DAG the chain nodes are the first operands for you custom nodes, however for the other nodes the chain is the last operand. I seem to remember that during targetlowering the chain is the first operand and then it seems to switch over after ISelDAG, this confused me and may have something to do with the issue that you are seeing. I really don't

...ag to MemSDNode to mark instructions where movnt (on x86) and other goodness can happen (we'll also add the TableGen patterns to properly select movnt). In our tree we simply added another flag to the MemSDNode constructor and embedded it in SubclassData: MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT, const Value *srcValue, int SVOff, unsigned alignment, bool isvolatile, bool NonTemporal); This is ugly for a variety of reasons and also doesn't scale as we want to add more of this kind of information. So what if we replace Volatile/NonTemporal with...

...lectionDAGBuilder::visitIntrinsicCall in lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp and SelectionDAGBuilder::visitTargetIntrinsic in the same file. in visitTargetIntrinsic, ComputeValueVTs acts as a barrier which strips type information out from CallInst ("I"), and leave SDValue and SDVTList ("Ops" and "VTs") to target code. SDValue and SDVTList are wrappers of EVT and MVT, all information we concern won't be passed here. I think now we have 2 choices: 1. Hacking into clang, implement target specific builtin function. Now I have worked out a ugly but worka...

...f8062d35a _sigtramp + 26 3 libSystem.B.dylib 0x0000000101612d10 _sigtramp + 2164152784 4 clang 0x0000000100018aa6 abort + 22 5 clang 0x0000000100018a68 __assert_rtn + 56 6 clang 0x000000010093a64e llvm::MemSDNode::MemSDNode(unsigned int, llvm::DebugLoc, llvm::SDVTList, llvm::SDValue const*, unsigned int, llvm::EVT, llvm::MachineMemOperand*) + 190 7 clang 0x0000000100933ec7 llvm::SelectionDAG::getMemIntrinsicNode(unsigned int, llvm::DebugLoc, llvm::SDVTList, llvm::SDValue const*, unsigned int, llvm::EVT, llvm::MachineMemOperand*) + 519 8 clang...

...+ 26 > 3 libSystem.B.dylib 0x0000000101612d10 _sigtramp + 2164152784 > 4 clang 0x0000000100018aa6 abort + 22 > 5 clang 0x0000000100018a68 __assert_rtn + 56 > 6 clang 0x000000010093a64e llvm::MemSDNode::MemSDNode(unsigned int, llvm::DebugLoc, llvm::SDVTList, llvm::SDValue const*, unsigned int, llvm::EVT, llvm::MachineMemOperand*) + 190 > 7 clang 0x0000000100933ec7 llvm::SelectionDAG::getMemIntrinsicNode(unsigned int, llvm::DebugLoc, llvm::SDVTList, llvm::SDValue const*, unsigned int, llvm::EVT, llvm::MachineMemOperand*) + 519 > 8 c...

...p.getOperand(1); unsigned MULHXOpcode = Opc == ISD::UMUL_LOHI ? ISD::MULHU : ISD::MULHS; SDValue res[2] = { // Seems wasteful to generate both of these twice per node DAG.getNode(ISD::MUL, dl, VT, Op0, Op1), LowerMULHX(DAG.getNode(MULHXOpcode, dl, VT, Op0, Op1), DAG), }; SDVTList VTs = DAG.getVTList(VT, VT); SDNode * N = DAG.getNode(ISD::MERGE_VALUES, dl, VTs, res[0], res[1]).getNode(); return SDValue(N,Op.getResNo()); // AArch64 doesn’t do this } The above is weird in at least two respects. It generates an ISD::MUL when ResNo == 1, which will then be dropped e...

...e movnt (on x86) and other > goodness > can happen (we'll also add the TableGen patterns to properly select > movnt). > > In our tree we simply added another flag to the MemSDNode constructor > and embedded it in SubclassData: > > MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT, > const Value *srcValue, int SVOff, > unsigned alignment, bool isvolatile, bool NonTemporal); > > This is ugly for a variety of reasons and also doesn't scale as we > want to add more of this kind of information. > > So what if we re...

I'm trying to replace SDIvRem (whch returns two i16 types) with a custom that returns i32 or i16. I am getting the Assertion (!Node || ResNo < Node->getNumValues() && "Invalid result number for the given node!") Seems that it doesn't like returning one value but how do you return more than one value? I am doing this in the LowerOperation for the case SDIVREM and a

Hello. I fixed the bug reported in the previous post on this thread (<<llvm::MemSDNode::MemSDNode(unsigned int, unsigned int, const llvm::DebugLoc&, llvm::SDVTList, llvm::EVT, llvm::MachineMemOperand*): Assertion `memvt.getStoreSize() <= MMO->getSize() && "Size mismatch!"' failed.>>) The problem with this strange error reported comes from the fact I actually did NOT have defined type v128i64 in files: [repo]/llv...

...e movnt (on x86) and other > goodness > can happen (we'll also add the TableGen patterns to properly select > movnt). > > In our tree we simply added another flag to the MemSDNode constructor > and embedded it in SubclassData: > > MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT MemoryVT, > const Value *srcValue, int SVOff, > unsigned alignment, bool isvolatile, bool NonTemporal); > > This is ugly for a variety of reasons and also doesn't scale as we > want to add more of this kind of information. > > So what if we re...

Hi, I have implemented a pair intrinsic nodes in back-end, But there is a chain dependence between two intrinsic nodes. So in the Pre-RA-sched stage, these two intrinsic nodes would be apart. I expect that there is no node between these two intrinsic nodes, therefore, I guess it would be work if there is a MVT::Glue between these nodes. But I don’t know how to add. Thanks in advance. Haishan

...lli 0x0873f704 8 lli 0x08597416 X86CompilationCallback2 + 166 9 lli 0x08596e08 X86CompilationCallback + 24 10 lli 0x00eebff5 X86CompilationCallback + 4170535429 11 lli 0x0863e13e llvm::CallSDNode::CallSDNode(unsigned int, llvm::DebugLoc, bool, bool, bool, llvm::SDVTList, llvm::SDValue const*, unsigned int, unsigned int) + 90 12 lli 0x08622d47 llvm::SelectionDAG::getCall(unsigned int, llvm::DebugLoc, bool, bool, bool, llvm::SDVTList, llvm::SDValue const*, unsigned int, unsigned int) + 419 13 lli 0x08648853 llvm::TargetLowering::LowerCallTo(llvm::SDVal...

...16,ch = masked_gather<LD128[<unknown>](align=256)> t0, t130, t193, TargetConstant:i64<0>, t121 llc: /home/asusu/LLVM/llvm38Nov2016/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:6804: llvm::MemSDNode::MemSDNode(unsigned int, unsigned int, const llvm::DebugLoc&, llvm::SDVTList, llvm::EVT, llvm::MachineMemOperand*): Assertion `memvt.getStoreSize() <= MMO->getSize() && "Size mismatch!"' failed. Does anybody know why this happens? I'd like to mention that I also gave in [Target]ISelLowering.cpp a call to setOperationAction(ISD::MGATHE...

...+2727,13 @@ SDOperand Ptr = Op.getOperand(1); SDOperand Incr = Op.getOperand(2); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Label + Chain, + Ptr, + Incr, }; - SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3); - Chain = Load.getValue(1); - - //...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...+2727,13 @@ SDOperand Ptr = Op.getOperand(1); SDOperand Incr = Op.getOperand(2); - // Issue a "load and reserve". - std::vector<MVT> VTs; - VTs.push_back(VT); - VTs.push_back(MVT::Other); - - SDOperand Label = DAG.getConstant(PPCAtomicLabelIndex++, MVT::i32); + SDVTList VTs = DAG.getVTList(VT, MVT::Other); SDOperand Ops[] = { - Chain, // Chain - Ptr, // Ptr - Label, // Label + Chain, + Ptr, + Incr, }; - SDOperand Load = DAG.getNode(PPCISD::LARX, VTs, Ops, 3); - Chain = Load.getValue(1); - - //...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Hello everyone, I wanted to attach a node without affecting the present nodes in any way. I tried to use MVT::Glue for that but I think I'm missing something as I could not achieve the below state. LUI LUI | | ADDI ----GLUE---- ADDI | store I've few question about this and Glue node in general, I'll be happy to get some help on

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it: