Displaying 20 results from an estimated 484 matches for "sdvalues".
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2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 5:26 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
>> Can you explain why you chose the approach of using a new pass?
>> I pictured removing LegalizeDAG's type legalization code would
>> mostly consist of finding all the places that use TLI.getTypeAction
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
Please tell me whether the following implementation is correct.....
My target supports 64 bit mask means immediate(0-2^63)
I have implemented it but i dont know whether its correct or not. Please
see the changes below that i have made in x86isellowering.cpp
static SDValue lower2048BitVectorShuffle(const SDLoc &DL, ArrayRef<int>
Mask,
MVT VT,
2013 Mar 04
1
[LLVMdev] Custom Lowering of ARM zero-extending loads
Hi,
For my research, I need to reshape the current ARM backend to support
armv2a. Zero-extend half word load (ldrh) is not supported by armv2a, so I
need to make the code generation to not generate ldrh instructions. I want
to replace all those instances with a 32-bit load (ldr) and then and the
result with 0xffff to mask out the upper bits.
These are the modifications that I have made to
2016 Jan 22
3
Return value from TargetLowering::LowerOperation?
Hi,
I'm a litle bit puzzled by the TargetLowering::LowerOperation function,
and what different callers of this function assumes about the returned
value.
In several places it seems like it is assumed that LowerOperation can
return three kinds of values:
* Something completely new.
* SDValue()
* The same SDValue as LowerOperation was called on.
However in some places, e.g. in
2008 Dec 09
1
[LLVMdev] [PATH] Add sub.ovf/mul.ovf intrinsics
Hi,
The attached patch implements sub.ovf/mul.ovf intrinsics similarly to
the recently added add.ovf intrinsics. These are useful for
implementing some vm instructions like sub.ovf/mul.ovf in .NET IL
efficiently. sub.ovf is supported in target independent lowering and
on x86, while mul.ovf is only supported in the x86 backend.
Please review
2009 Feb 17
1
[LLVMdev] ARM backend playing with alternative jump table implementations
Hi list:
I have been trying to get my feet wet with the ARM backend.
As a warmup exercise I wanted to be able to move
jumptables especially large ones out of the code section.
Currently the idiom for jump tables loooks like this
// .set PCRELV0, (.LJTI9_0_0-(.LPCRELL0+8))
// .LPCRELL0:
// add r3, pc, #PCRELV0
// ldr pc, [r3, +r0, lsl #2]
// .LJTI9_0_0:
//
2014 Jul 11
2
[LLVMdev] Lowering to return multiple values: codeGen, instruction write one value to the input register.
Hi All,
In XCore backend, I saw
“
…...
EVT VT = Op.getValueType();
SDValue Data =
DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT),
Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3));
SDValue Crc(Data.getNode(), 1);
SDValue Results[] = { Crc, Data };
return DAG.getMergeValues(Results, 2, DL);
“ which is used to lower an
2016 Jan 25
1
Return value from TargetLowering::LowerOperation?
Hi,
On 01/22/2016 05:02 PM, Tom Stellard wrote:
> On Fri, Jan 22, 2016 at 01:58:49PM +0100, Mikael Holmén via llvm-dev wrote:
>> Hi,
>>
>> I'm a litle bit puzzled by the TargetLowering::LowerOperation function,
>> and what different callers of this function assumes about the returned
>> value.
>>
> SelectionDAGLegalize::LegalizeOp() is your best
2015 Mar 09
2
[LLVMdev] LLVM Backend DAGToDAGISel INTRINSIC
I am currently working on DAGToDAGISel class for MIPS and am trying to
figure out a way to use INTRINSIC_W_CHAIN for an intrinsic which can return
a value.
My intrinsic is defined as:
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>;
i.e. it has four arguments and one return value
In DAGToDAGISel when I try to pass it with four arguments and
2016 Mar 28
0
RFC: atomic operations on SI+
On Fri, Mar 25, 2016 at 02:22:11PM -0400, Jan Vesely wrote:
> Hi Tom, Matt,
>
> I'm working on a project that needs few coherent atomic operations (HSA
> mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
>
> the attached patch implements atomic compare and swap for SI+
> (untested). I tried to stay within what was available, but there are
> few issues
2011 Mar 24
0
[LLVMdev] mblaze backend: unreachable executed
> what does "refuses to compile" mean? I.e. what error do you get?
>
Specifically I get this message when compiling with the default -mattr:
Call result #2 has unhandled type i32
UNREACHABLE executed at CallingConvLower.cpp:162!
0 llc 0x0000000100a1e115 PrintStackTrace(void*) + 38
1 llc 0x0000000100a1e6d0 SignalHandler(int) + 254
2
2016 Mar 25
2
RFC: atomic operations on SI+
Hi Tom, Matt,
I'm working on a project that needs few coherent atomic operations (HSA
mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
the attached patch implements atomic compare and swap for SI+
(untested). I tried to stay within what was available, but there are
few issues that I was unsure how to address:
1.) it currently uses v2i32 for both input and output. This
2017 Jul 29
2
ISelDAGToDAG breaks node ordering
Hi,
During instruction selection, I have the following code for certain LOAD
instructions:
const LoadSDNode *LD = cast<LoadSDNode>(N);
SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT,
PtrVT, MVT::Other,
LD->getBasePtr(), LD->getChain());
// Honestly, I have no idea what this does, but other memory
// accessing instructions
2012 Aug 19
1
[LLVMdev] MBlaze select_cc lowering question.
Can someone explain how the condition code is passed from the
MBlazeTargetLowering::LowerSELECT_CC to
MBlazeTargetLowering::EmitCustomSelect custom inserter? In
LowerSELECT_CC the condition code is never accessed (Op.GetOperand(4))
and I don't see how it ends up getting correctly passed to the
MBlazeTargetLowering::EmitCustomSelect.
> SDValue
2009 Jul 02
1
[LLVMdev] [Help Needed] tblgen code get a compile error
I am working the AVR backend. It is still in the early stage. I got the
following error:[ 86%] Building CXX object
lib/Target/AVR/CMakeFiles/LLVMAVRCodeGen.dir/AVRISelDAGToDAG.cpp.obj
AVRISelDAGToDAG.cpp
C:\llvm-build\lib\Target\AVR\AVRGenDAGISel.inc(596) : error C2664:
'llvm::SDNode *llvm::SelectionDAG::SelectNodeTo(llvm::SDNode *,unsigned
int,llvm::MVT,llvm::MVT,llvm::MVT,const llvm::SDValue
2011 Mar 24
2
[LLVMdev] mblaze backend: unreachable executed
Hi Josef,
> Okay, I've done a lot more testing and I now have a .bc file that compiles for x86, sparc, mips but refuses to compile for the mblaze and powerPC backends because of the calling convention. Is there anyone that would know how to fix the microblaze calling convention or point me in the right direction on how to fix it?
what does "refuses to compile" mean? I.e. what
2017 Jan 23
2
returning from LowerOperation()
> On Jan 23, 2017, at 12:36, Friedman, Eli via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> On 1/23/2017 5:21 AM, Jonas Paulsson wrote:
>> Hi Eli,
>>
>> I would like to clarify generally what the difference is between returning SDValue() and Op (input argument unchanged) from LowerOperation()?
>>
>> My understanding is that returning SDValue()
2009 Jun 03
5
[LLVMdev] patch for llc/ARM: added mechanism to move switch tables from .text -> .data; also cleanup and documentation
Hi:
This is my first patch submission. Hopefully, this is the proper the protocol.
Attached is a patch for the llc ARM backend:
Added mechanism to generate switch table in a data section
rather than having it interleaved with the code.
This is controlled by command line flags and off by default.
Also, tried to document and improve the code where I modified it.
Robert
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