search for: sdtypeprofile

I noticed SDTypeProfile is commonly used with -1 for the number of operands, as in: def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; What does this do?

Hi, A piece of code in a target description file: def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> ]>; May I understand "SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>" as below? (Z = X + Y, for example); Z:0 X:1 Y:2 X has same type as Z...

On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote: > > On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote: > > def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; > > > I think for setting an implicit register, you still need to have 1 result > here. > > If you look at SDTX86CmpPTest, I think this is similar to what you are > trying to do. > > -Matt > def SDTX86CmpPTest : SDTypeProfile&l...

...I can't figure out what. >> >> Any help is appreciated. >> >> >> -- >> Rail Shafigulin >> Software Engineer >> Esencia Technologies >> >> >> >> What is SDT_EscalaSetFlag? >> >> > def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; > > > -- > Rail Shafigulin > Software Engineer > Esencia Technologies > Any recommendations? Would anyone be able to point out what am I missing? -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part ----...

...================================== --- lib/Target/PowerPC/PPCInstrInfo.td (revision 52957) +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -42,17 +42,23 @@ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; - -def SDT_PPClarx : SDTypeProfile<1, 2, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32> +def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [ + SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2> ]>; -def SDT_PPCstcx : SDTypeProfile<0, 3, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTC...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...================================== --- lib/Target/PowerPC/PPCInstrInfo.td (revision 53464) +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -42,17 +42,23 @@ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; - -def SDT_PPClarx : SDTypeProfile<1, 2, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32> +def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [ + SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2> ]>; -def SDT_PPCstcx : SDTypeProfile<0, 3, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTC...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...================================== --- lib/Target/PowerPC/PPCInstrInfo.td (revision 52957) +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -42,17 +42,23 @@ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; - -def SDT_PPClarx : SDTypeProfile<1, 2, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32> +def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [ + SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2> ]>; -def SDT_PPCstcx : SDTypeProfile<0, 3, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTC...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...el forms in instruction pattern should have void types The definitions it's complaining about: //===----------------------------------------------------------------------===// // RELADDR //===----------------------------------------------------------------------===// def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; let Uses= [GRP] in { def RelAddr : XSTGPseudo< (outs), (ins GPRC:$spoff, GPRC:$dst),...

...================================== --- lib/Target/PowerPC/PPCInstrInfo.td (revision 52957) +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -42,17 +42,23 @@ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; - -def SDT_PPClarx : SDTypeProfile<1, 2, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32> +def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [ + SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2> ]>; -def SDT_PPCstcx : SDTypeProfile<0, 3, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTC...

...EQ_START", SDT_MYCallSeqStart, [SDNPHasChain, SDNPOutGlue]>; def MYCallseqEnd : SDNode<"ISD::CALLSEQ_END", SDT_MYCallSeqEnd, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; def SDT_MYCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; def SDT_MYRet : SDTypeProfile<0, 0, []>; def MYcall : SDNode<"MYISD::CALL", SDT_MYCall, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; def MYret : S...

..., Phil Tomson wrote: > >> >> That's better, but now I get: >> >> XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires >> exactly 2 operands! >> >> Which makes some sense as XSTGRELADDR is defined as: >> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, >> SDTCisSameAs<0, 1>]>; >> def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; >> > > The problem is that the pattern that you use in the instruction definition > cannot have any value. That is, the top...

> > > > > def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, > SDTCisVec<1>, > SDTCisSameAs<2, 1>]>; > > This is confusing to me. This tells me that there is 1 result but and 2 > operands. But then it says that o...

...m XSTGRELADDR and try something like > [(set GPRC:$dst, (XSTGRELADDR GPRC:$spoff))] > > That's better, but now I get: XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires exactly 2 operands! Which makes some sense as XSTGRELADDR is defined as: def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>; Phil -Krzysztof > > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation > ________...