search for: sdtintunaryop

Displaying 5 results from an estimated 5 matches for "sdtintunaryop".

2018 Apr 09
2
Tablegen pattern: How to emit a SDNode in an output pattern?
...nstruction. The pattern I've written looks like the folowing: def : Pat<(foo (bar GPR:$rs1), simm12:$imm1), (bar (BAZ GPR:$rs1, simm12:$imm1))>; foo and bar are SDNodes, BAZ is an instruction. In particular, bar is defined as follows: def bar : SDNode<"ISD::BAR", SDTIntUnaryOp>; The basic idea of this pattern is to propagate bar over certain instructions until they reach a sink pattern, which only emits an instruction. However, it seems that SDNodes in output patterns are not supported, because when building LLVM, I get the following error message: error: In anonymo...
2009 Apr 20
0
[LLVMdev] A few questions from a newbie
...other is generated by tbglen following the pattern I specified. The > compilation fails because of the two duplicated and conflicting cases. This happened to me too. I stole a solution from the other targets - create a wrapper node: def BfinWrapper: SDNode<"BfinISD::Wrapper", SDTIntUnaryOp>; Then custom lower ISD::GlobalAddress, converting it to a wrapped TargetGlobalAddress: SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { DebugLoc DL = Op.getDebugLoc(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); O...
2009 Apr 20
2
[LLVMdev] A few questions from a newbie
Hello, I am learning to write a new backend for LLVM and have a few simple questions. 1) What are the differences between 'constant' and 'targetconstant', 'globaladdress' and 'targetglobaladdress'? It is not clear from the document when and which should be used. 2) On the processor I am working on, there is a 'move reg, mem_addr' instruction. When I try
2009 Apr 20
2
[LLVMdev] A few questions from a newbie
...bglen following the pattern I specified. The > > compilation fails because of the two duplicated and conflicting cases. > > This happened to me too. I stole a solution from the other targets - > create a wrapper node: > > def BfinWrapper: SDNode<"BfinISD::Wrapper", SDTIntUnaryOp>; > > Then custom lower ISD::GlobalAddress, converting it to a wrapped > TargetGlobalAddress: > > SDValue > BlackfinTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG > &DAG) > { > DebugLoc DL = Op.getDebugLoc(); > GlobalValue *GV = cast<GlobalAd...
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...NPAssociative] > +>; > + > +// urecip - This operation is a helper for integer division, it returns the > +// result of 1 / a as a fractional unsigned integer. > +// out = (2^32 / a) + e > +// e is rounding error > +def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>; > > Added: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=160270&view=auto > ============================================================================== > --- llvm/trunk...