Displaying 3 results from an estimated 3 matches for "sdtil_binatomnoret".
2010 Nov 08
2
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...ve intrinsic with no return value and I need to match them to machine instructions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted.
Here is my profile/node/pattern.
Profile:
def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [
SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
]>;
Node:
def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>;
Pattern:
def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,...
2010 Nov 08
0
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...NoRet<IL_OP_UAV_ADD,
"_id($id)", atom_g_add_noret>;
For an existing example, have a look at the memory barrier instruction definitions for the ARM target (DMB and DMB_MCR in ARMInstrInfo.td).
Regards,
Jim
>
> Here is my profile/node/pattern.
> Profile:
> def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [
> SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
> ]>;
> Node:
> def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>;
>
> Pattern:
> def ATOM_G_ADD_NORET...
2010 Nov 08
1
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...erge_values:
0x8503160: i32,ch = AMDILISD::ATOM_G_ADD_NORET 0x8502a78, 0x8502280, 0x8502eb8, 0x8502f40
I probably have other issues, but solving this should help me solve other issues.
Thanks again,
Micah
>
> >
> > Here is my profile/node/pattern.
> > Profile:
> > def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [
> > SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
> > ]>;
> > Node:
> > def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET",
> SDTIL_BinAtomNoRet, [SDNPHasChain]>;
> >
> > Patt...