Displaying 20 results from an estimated 46 matches for "sdtcissamea".
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sdtcissameas
2016 Feb 03
2
New register class and patterns
On Tue, Feb 2, 2016 at 8:42 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>
> On Feb 2, 2016, at 16:52, Rail Shafigulin <rail at esenciatech.com> wrote:
>
> def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
>
>
> I think for setting an implicit register, you still need to have 1 result
> here.
>
> If you look at SDTX86CmpPTest, I think this is similar to what you are
> trying to do.
>
> -Matt
>
def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0...
2009 Nov 30
1
[LLVMdev] Description of SDTypeProfile
Hi,
A piece of code in a target description file:
def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
]>;
May I understand "SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>" as
below?
(Z = X + Y, for example);
Z:0
X:1
Y:2
X has same type as Z
Y has same type as Z
Z is a integer
Thanks
-------------- n...
2016 Feb 03
2
New register class and patterns
...what.
>>
>> Any help is appreciated.
>>
>>
>> --
>> Rail Shafigulin
>> Software Engineer
>> Esencia Technologies
>>
>>
>>
>> What is SDT_EscalaSetFlag?
>>
>>
> def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
>
>
> --
> Rail Shafigulin
> Software Engineer
> Esencia Technologies
>
Any recommendations? Would anyone be able to point out what am I missing?
--
Rail Shafigulin
Software Engineer
Esencia Technologies
-------------- next part --------------
An HTML att...
2018 Jul 10
2
Stuck with instruction in tablegen
2016 Feb 04
2
New register class and patterns
>
>
>
>
> def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
> SDTCisVec<1>,
> SDTCisSameAs<2, 1>]>;
>
> This is confusing to me. This tells me that there is 1 result but and 2
> operands. But then it says that operands 2 and 1 are of the same type,
> SDTCisSameAs<2, 1>. Given that operand numbering starts at 0, how can there
> be operands 2 and 1?
>
>...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...s better, but now I get:
>>
>> XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires
>> exactly 2 operands!
>>
>> Which makes some sense as XSTGRELADDR is defined as:
>> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>,
>> SDTCisSameAs<0, 1>]>;
>> def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
>>
>
> The problem is that the pattern that you use in the instruction definition
> cannot have any value. That is, the top node has to consume all values
> produced by th...
2018 Jul 10
2
Stuck with instruction in tablegen
...(Z80add_flag
A, (i8 (load iPTR:$src))))]>;
}
}
and the parameters:
def SDTBinOpRF : SDTypeProfile<2, 2, [SDTCisInt<0>,
SDTCisFlag<1>,
SDTCisSameAs<2, 0>,
SDTCisSameAs<3, 0>]>;
def Z80add_flag : SDNode<"Z80ISD::ADD", SDTBinOpRF,
[SDNPCommutative]>;
The unary instruction builds fine, which can be checked by commenting
out the generation of the binary...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...set GPRC:$dst, (XSTGRELADDR GPRC:$spoff))]
>
>
That's better, but now I get:
XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires
exactly 2 operands!
Which makes some sense as XSTGRELADDR is defined as:
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,
1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
Phil
-Krzysztof
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
> _______________________________________________
&g...
2008 Dec 05
2
[LLVMdev] (tablegen) Machine instruction without result
...y modelized. Therefore, I suspect my tablegen description of this instruction to be erroneous, so I paste it below with comments what I think I am doing:
//define an instruction profile with zero results,
//2 inputs which are of the same type (int)
def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
SDTCisSameAs<0, 1>, SDTCisInt<0>
]>;
//define a node using that profile with a OutFlag
//property (which is a way to modelise e.g. HW internal CC registers?)
def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp, [SDNPOutFlag]>;
//define the instruction
def MYcmp : InstMYAr...
2008 Sep 12
2
[LLVMdev] Selection Condition Codes
...lt;dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "Inst";
dag OutOperandList = outs;
dag InOperandList = ins;
let Pattern = pattern;
let AsmString = asmstr;
}
def SDTGenTernaryOp : SDTypeProfile<1, 3, [ SDTCisSameAs<0,
1>,SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3> ]>;
def cmov_logical : SDNode<"INSTISD::CMOVLOG", SDTGenTernaryOp>;
let PrintMethod = "printCCOperand" in
def CCOp : Operand<i32>;
def CMOVLOG : InstFormat<(outs GPR:$dst), (ins GPR:$LH...
2016 Jan 08
2
TableGen error message: top-level forms in instruction pattern should have void types
On 1/7/2016 5:54 PM, Phil Tomson wrote:
> I got it to compile by changing to:
> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>,
> SDTCisSameAs<0, 1>]>;
> def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
>
> let Uses= [GRP] in {
> def RelAddr : XSTGPseudo< (outs GPRC:$dst),
> (ins GPRC:$spoff, GPRC:$addr),
>...
2009 Feb 19
1
[LLVMdev] help: about how to use tblgen to constraint operand.
I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.
But I need to use an even/odd register pair to save its 2 operands.
I define in mytarget.td:
myfmdrr:
SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
(outs FPR: $result), ins(GPR: $op1, GPR:$op2 )
[(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )]
I create myfmdrr instructure in mytargetISelLowering.cpp. and its operands are in R0 and...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...void
types
The definitions it's complaining about:
//===----------------------------------------------------------------------===//
// RELADDR
//===----------------------------------------------------------------------===//
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,
1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
let Uses= [GRP] in {
def RelAddr : XSTGPseudo< (outs),
(ins GPRC:$spoff, GPRC:$dst),
"! RELADDR $spoff...
2016 Feb 02
2
New register class and patterns
> On Feb 1, 2016, at 16:53, Rail Shafigulin <rail at esenciatech.com> wrote:
>
>
>
> On Fri, Jan 29, 2016 at 10:03 PM, Matt Arsenault <arsenm2 at gmail.com <mailto:arsenm2 at gmail.com>> wrote:
>
> > On Jan 29, 2016, at 13:25, Rail Shafigulin via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
> >
>
2016 Feb 22
2
Failure to match a DAG after a minor pattern change in a custom Target
On Fri, Feb 19, 2016 at 6:10 AM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 2/18/2016 6:01 PM, Rail Shafigulin via llvm-dev wrote:
>
>> [(set SR:$rD, (Esenciasetflag (i32 GPR:$rA), (i32
>> immSExt16:$imm), (i32 Cond)))]> {
>>
>
> I suspect that the "set SR:$rD" is the problem here. The Esenciasetflag
2010 Aug 04
2
[LLVMdev] x86 Vector Shuffle Patterns
...X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
}], SHUFFLE_get_shuf_imm>;
First off, why does the vector_shuffle pattern take only two operands?
I understand that the VECTOR_SHUFFLE node has three operands but
vector_shuffle is defined as:
def SDTVecShuffle : SDTypeProfile<1, 2, [
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
]>;
def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
So the pattern match is against the two input vectors, excluding the
shuffle mask. Why is this?
In the SHUFPS above the shuffle mask is annotated into the shufp
o...
2008 Dec 05
0
[LLVMdev] (tablegen) Machine instruction without result
...tablegen description of this instruction to
> be erroneous, so I paste it below with comments what I think I am
> doing:
>
> //define an instruction profile with zero results,
> //2 inputs which are of the same type (int)
> def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
> SDTCisSameAs<0, 1>, SDTCisInt<0>
> ]>;
>
> //define a node using that profile with a OutFlag
> //property (which is a way to modelise e.g. HW internal CC registers?)
> def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp,
> [SDNPOutFlag]>;
>
>
> /...
2013 Jan 04
2
[LLVMdev] TableGen patterns with multiple outputs
Are multi-output patterns in TableGen supposed to work, or is that a known
limitation in the current implementation?
If I have TableGen code like the following...
1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>;
1244
1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1),
1246 (ins Int32Regs:$a),
1247 "test $dst0, $dst1, $a;",...
2013 Jan 07
2
[LLVMdev] TableGen patterns with multiple outputs
...or is that a known
> limitation in the current implementation?
>
>
> It is a known limitation. You have to write C++ code to match patterns
> with multiple outputs.
>
>
> If I have TableGen code like the following...
>
> 1242 def SDTTestNode : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
> 1243 def TestNode : SDNode<"NVPTXISD::TestNode", SDTTestNode>;
> 1244
> 1245 def MyTestNode : NVPTXInst<(outs Int32Regs:$dst0, Int32Regs:$dst1),
> 1246 (ins Int32Regs:$a),
> 1247 "test...
2009 Feb 20
2
[LLVMdev] help: about how to use tblgen to constraint operand.
...19, 2009, at 2:00 AM, 任坤 wrote:
I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr.
But I need to use an even/odd register pair to save its 2 operands.
I define in mytarget.td:
myfmdrr:
SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def my_fmdrr : ...........
def myFMDRR : ....
(outs FPR: $result), ins(GPR: $op1, GPR:$op2 )
[(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )]
I create myfmdrr instructure in mytargetISelLowering.cpp. and its operands are in R0 and...