Displaying 6 results from an estimated 6 matches for "sdsuboperand".
2007 Apr 24
2
[LLVMdev] Register based vector insert/extract
...me suggestions about 2 posts back <http://
lists.cs.uiuc.edu/pipermail/llvmdev/2007-April/008834.html>
He mentioned that the place where the constraint would need to be
enforced was during the register rewriting pass.
My first productive thoughts were to create a subclass of SDOperand
(SDSubOperand) that Lowering could use to communicate the target
specific subregister index. The other thought was to have something
akin to "getSubRegisterForIndex()" in MRegisterInfo, which would
return a sub register of the correct type at the specified index in a
target dependent way. I'...
2007 Apr 24
0
[LLVMdev] Register based vector insert/extract
...back <http://
> lists.cs.uiuc.edu/pipermail/llvmdev/2007-April/008834.html>
>
> He mentioned that the place where the constraint would need to be
> enforced was during the register rewriting pass.
>
> My first productive thoughts were to create a subclass of SDOperand
> (SDSubOperand) that Lowering could use to communicate the target
> specific subregister index. The other thought was to have something
> akin to "getSubRegisterForIndex()" in MRegisterInfo, which would
> return a sub register of the correct type at the specified index in a
> target dependen...
2007 Jun 06
2
[LLVMdev] Register based vector insert/extract
...g
> nodes)
> currently thinks of register operands as simple unsigned's for
> vreg
> #'s. This needs to be extended to be vreg+subreg pairs (see
> 'CreateVirtualRegisters').
> 5. We need to decide how to represent subregs in the DAG. Your
> SDSubOperand idea is fine, but I don't think it needs to be an
> actual
> new subclass of SDOperand. Instead, it could just be a binary
> SDNode,
> where the LHS is the register input and the RHS is a
> TargetConstant
> specifying the subreg#.
> 6. [optional] We would...
2007 Jun 06
0
[LLVMdev] Register based vector insert/extract
...currently thinks of register operands as simple unsigned's for
>> vreg
>> #'s. This needs to be extended to be vreg+subreg pairs (see
>> 'CreateVirtualRegisters').
>> 5. We need to decide how to represent subregs in the DAG. Your
>> SDSubOperand idea is fine, but I don't think it needs to be an
>> actual
>> new subclass of SDOperand. Instead, it could just be a binary
>> SDNode,
>> where the LHS is the register input and the RHS is a
>> TargetConstant
>> specifying the subreg#.
>...
2007 Apr 24
0
[LLVMdev] Register based vector insert/extract
On Apr 23, 2007, at 4:07 PM, Christopher Lamb wrote:
> Thanks for the detailed response.
>
> On Apr 23, 2007, at 4:22 PM, Chris Lattner wrote:
>
>> Right. Evan is currently focusing on getting the late stages of
>> the code
>> generator (e.g. livevars) to be able to understand arbitrary machine
>> instrs in the face of physreg subregs. This lays the
2007 Apr 23
2
[LLVMdev] Register based vector insert/extract
Thanks for the detailed response.
On Apr 23, 2007, at 4:22 PM, Chris Lattner wrote:
> Right. Evan is currently focusing on getting the late stages of
> the code
> generator (e.g. livevars) to be able to understand arbitrary machine
> instrs in the face of physreg subregs. This lays the groundwork for
> handling vreg subregs, but won't solve it directly.
Is the work Evan